Thick Metal Interconnects for Semiconductor Chip RC Delay Reduction
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Solution Overview
Problem
The challenge in semiconductor chip design is to form thick metal layers without incurring significant inner stress and cost, while existing methods like damascene copper processes are limited by the thickness of copper traces and the cost of forming thick aluminum layers.
Innovation Solution
A semiconductor chip structure with a redistribution circuit layer and a polymer layer over a passivation layer, using wide and thick metal lines to reduce RC Delay, and forming inductors, capacitors, and resistors with a thick metal layer, allowing for thicker metal interconnections and improved connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If thick metal layers are formed using conventional methods (sputtering aluminum or damascene copper), then the metal layer thickness can be increased, but the inner stress and manufacturing cost increase significantly
Solution Approach 1:
The patent divides the thick metal layer formation into multiple thin film deposition steps, where each step deposits a thin layer (e.g., 50-200nm) that is then patterned and etched. This segmentation allows the total thickness to be built up incrementally without the stress and cost issues of forming a single thick layer, as each thin layer can be controlled independently with standard sputtering equipment.
Solution Approach 2:
The patent transitions from forming thick metal layers in the vertical dimension (single thick layer) to building thickness through repeated cycles of thin layer deposition and patterning in the horizontal process dimension. This dimensional shift in the manufacturing approach enables thick metal layers to be achieved through process iteration rather than single-step thick deposition.
2Reliability
If wider metal lines are used to reduce resistance, then the resistance decreases, but the parasitic capacitance increases
Solution Approach 1:
The patent changes the physical parameters of the metal interconnections by forming thick metal layers (increased thickness parameter) which reduces resistance without requiring increased lateral width. This parameter change in the vertical dimension (thickness) allows resistance reduction while avoiding the parasitic capacitance penalty that would result from increasing the horizontal dimensions of the metal lines.
3Length of stationary object
If aluminum layers thicker than 2 microns are formed by sputtering, then the metal layer thickness can be increased, but the process becomes very difficult and expensive
Solution Approach 1:
The patent segments the thick aluminum layer formation into multiple thin film deposition steps, where each step deposits a manageable thin layer (e.g., 50-200nm) that can be formed using standard sputtering equipment without excessive stress or cost. The total thickness is achieved through repeated cycles of thin layer deposition, patterning, and etching, making the process feasible with conventional equipment.
Solution Approach 2:
The patent applies partial action by forming thin aluminum layers incrementally rather than attempting to form the complete thick layer in a single deposition step. Each thin layer is deposited to a controlled thickness that is well within the capabilities of standard sputtering equipment, and the process is repeated until the desired total thickness is achieved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of thick metal layers with reduced parasitic capacitance and resistance, enhancing chip performance by improving signal transmission and reducing the impact of parasitic capacitance, while being cost-effective and technologically feasible.
Implementation Method 1
An aluminum thin-film layer is formed to cover the whole chip by using a sputtering process
Implementation Method 2
a copper layer is formed by an electroplating process inside the opening in the insulating layer and on the insulating layer
Implementation Method 3
the copper layer outside the opening in the insulating layer is removed by using a Chemical Mechanical Polishing/Planarization (CMP)
Implementation Method 4
a dielectric material with low dielectric constant (k) is used between the signal lines
Data Source
AI summary
A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second MOS device, a passivation layer over said first and second MOS devices and over said first and second metallization structures, and a third metallization structure connecting said first and second metallization structures.