Thick-Oxide Power Gating for FPGA Leakage Current Reduction
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Solution Overview
Problem
Current FPGA architectures lack effective power management capabilities, leading to excessive power consumption in standby mode, especially in battery-powered applications, due to high leakage current exacerbated by advancing semiconductor technologies.
Innovation Solution
The use of power gating transistors with thicker gate oxides is implemented to reduce leakage current, along with additional circuitry to prevent short-circuit currents, and strategic placement of these transistors adjacent to memory cell blocks to provide programmable power connections, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional power gating transistors are used in logic core, then power consumption is reduced, but leakage current reduction is limited due to advancing processing technologies
Solution Approach 1:
The patent extracts power gating transistors from the logic core and relocates them to the interconnect structure between logic blocks. This separation allows the use of independently optimized transistor geometries - thick-oxide transistors for power gating functions - without compromising logic core performance or area.
Solution Approach 2:
The patent applies different oxide thicknesses to different locations: thick-oxide transistors are used specifically for power gating functions where leakage reduction is critical, while thin-oxide transistors remain in the logic core for high-speed operation. This localized quality differentiation optimizes both power management and logic performance.
2Quantity of substance
If transistor geometries are scaled down for advanced semiconductor processing, then device density is improved, but leakage power increases
Solution Approach 1:
The patent changes the oxide thickness parameter specifically for power gating transistors, using thick-oxide devices instead of scaled-down thin-oxide devices. This parameter change in the power gating layer reduces leakage current while allowing the logic core to continue using scaled geometries for high density.
3Adaptability or versatility
If FPGAs are used in battery-powered applications, then programmability is provided, but standby power consumption exceeds requirements
Solution Approach 1:
The patent segments the FPGA architecture into independently power-gated logic blocks, each with its own thick-oxide power gating transistor. This segmentation allows individual blocks to be powered down independently during standby mode, significantly reducing total standby power consumption while maintaining programmability.
4Loss of energy
If additional circuitry is added to prevent short-circuit currents, then leakage reduction is improved, but device complexity increases
Solution Approach 1:
The patent merges the power gating function with the interconnect structure by placing thick-oxide transistors directly in the interconnect routing between logic blocks. This integration combines power management with the existing interconnect architecture, reducing the need for separate power gating circuits and minimizing additional complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces leakage current and power consumption, enabling FPGAs to be more suitable for low-power applications by isolating inactive logic blocks from power supply connections and providing virtual power connections to active blocks, thus extending battery life in mobile devices.
Implementation Method 1
The first transistor exhibits a thicker gate oxide relative to transistors of the first logic block. The second transistor exhibits a thicker gate oxide relative to transistors of the second logic block.
Data Source
AI summary
Leakage current reduction from a logic block is implemented via power gating transistors that exhibit increased gate oxide thickness as compared to the thin-oxide devices of the power gated logic block. Increased gate oxide further allows increased gate to source voltage differences to exist on the power gating devices, which enhances performance and reduces gate leakage even further. Placement of the power gating transistors in proximity to other increased gate oxide devices minimizes area penalties caused by physical design constraints of the semiconductor die.