Thick Metal Pad and Bump Layout for Low-Resistance Semiconductor Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The configuration of protective insulating layers and bumps in semiconductor devices leads to increased contact resistance and bonding defects, affecting current drivability and signal transmission rates.
Innovation Solution
A semiconductor device design featuring an interlayer insulating layer with middle interconnections, a pad, an upper interconnection, and a protective insulating layer with a specific thickness and gap configuration, where the bump extends over the upper interconnection, ensuring a planar surface and improved electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional protective insulating layer configuration is used, then the device structure is simple, but contact resistance increases and bonding defects occur
Solution Approach 1:
The protective insulating layer is divided into multiple segments: a first protective insulating layer covering the pad edge, a second protective insulating layer covering the upper interconnection, and a third protective insulating layer filling the gap between them. This segmentation allows each layer to be optimized for its specific function, reducing contact resistance while maintaining structural clarity.
Solution Approach 2:
Different regions of the protective insulating structure are assigned different properties and thicknesses. The first protective insulating layer has specific thickness parameters (1μm to 5μm) optimized for pad edge protection, while the gap-filling third layer is optimized for stress relief and electrical isolation. This local optimization resolves the contradiction by improving reliability in critical areas without uniformly increasing complexity.
2Reliability
If the pad thickness is increased to improve current drivability, then signal transmission rate improves, but the device structure becomes more complex
Solution Approach 1:
The pad thickness is optimized to specific parameter ranges (twice to 100 times the middle interconnection thickness, with absolute thickness of 1μm to 5μm). The gap length is also parameterized (1μm or more). These parameter changes improve current drivability and signal transmission while maintaining manufacturability and avoiding excessive complexity.
Solution Approach 2:
The solution moves from two-dimensional planar connections to three-dimensional stacked interconnections with vertical thickness variations. The pad extends vertically with controlled thickness, and the bump structure adds another vertical dimension, improving current capacity without increasing lateral footprint or overall structural complexity.
3Reliability
If the gap between pad and upper interconnection is increased to reduce interference, then signal transmission rate improves, but manufacturing precision requirements increase
Solution Approach 1:
The third protective insulating layer acts as an intermediary material filling the gap between the pad and upper interconnection. This mediator provides electrical isolation and stress relief while defining the gap dimension through its own thickness parameter, thereby reducing the precision requirements for directly controlling the gap between conductive elements.
Solution Approach 2:
The gap length is parameterized with a minimum value (1μm or more), providing design flexibility. By setting a reasonable minimum gap parameter, the invention achieves signal transmission improvement while keeping manufacturing precision requirements within practical limits through the use of the insulating layer as a dimensional reference.
Data Source
AI summary
A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.