Thick-Source/Drain ITO Transistors for Low Parasitic Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturizing transistors further due to high contact resistance between metal and thin film oxide semiconductors, which hinders the integration of thin film transistors (TFTs) in the back-end-of-line (BEOL) for increased areal density and functionality, as current TFTs have insufficient switching speed for core logic tasks.
Innovation Solution
The use of a transistor structure combining thick Indium-Tin-Oxide (ITO) layers for metallic properties and thin ITO layers for semiconducting properties to form TFTs with low parasitic resistance, along with the application of other oxides like Indium-Gallium-Zinc-Oxide (IGZO), optimizing the channel independent of source/drain design, and not requiring doping for active regions, to create a scalable thin film transistor architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thin film oxide semiconductors are used to enable low-temperature processing and BEOL integration, then manufacturing compatibility is improved, but contact resistance between metal and semiconductor increases
Solution Approach 1:
The patent employs a composite material structure consisting of multiple oxide semiconductor layers with different thicknesses and compositions. A thin oxide semiconductor layer (2-10 nm) provides semiconducting properties for the channel, while thicker oxide semiconductor regions (15-50 nm) in the source/drain areas provide metallic properties for low contact resistance. This composite approach allows simultaneous achievement of low-temperature processing compatibility and reduced contact resistance.
Solution Approach 2:
The patent applies local quality by varying the thickness and composition of oxide semiconductor layers across different device regions. The channel region uses a thin oxide semiconductor layer optimized for semiconducting behavior, while the source and drain regions use thicker oxide semiconductor layers that exhibit metallic properties. This spatial variation in material properties resolves the contradiction between needing low contact resistance at contacts and maintaining semiconducting behavior in the channel.
2Productivity
If transistor size is reduced to increase areal density, then productivity is improved, but switching speed deteriorates due to high contact resistance
Solution Approach 1:
The multi-layer oxide semiconductor structure with varying thicknesses enables simultaneous achievement of miniaturization and maintained switching speed. The thicker oxide semiconductor regions in source/drain areas provide low contact resistance even in scaled devices, while the thin channel region maintains proper semiconducting behavior, enabling fast switching in small-footprint transistors.
Solution Approach 2:
The patent changes the thickness parameter of oxide semiconductor layers to optimize device performance at different locations. By adjusting the oxide semiconductor thickness from 2-10 nm in the channel to 15-50 nm in source/drain regions, the patent achieves proper balance between switching speed (requiring thin channel) and contact resistance (requiring thick source/drain), enabling scaled devices to maintain high switching speeds.
3Speed
If oxide semiconductor thickness is reduced to optimize channel properties, then switching speed is improved, but contact resistance increases
Solution Approach 1:
The patent applies local quality by using different oxide semiconductor layer thicknesses in different device regions. The channel region employs a thin oxide semiconductor layer (2-10 nm) optimized for fast switching, while the source and drain regions employ thicker oxide semiconductor layers (15-50 nm) that provide low contact resistance. This spatial differentiation resolves the contradiction between switching speed and contact resistance.
Solution Approach 2:
The patent uses a composite material approach with multiple oxide semiconductor layers having different thicknesses and properties. The thin oxide semiconductor channel provides fast switching, while the thicker oxide semiconductor source/drain regions provide low contact resistance. This composite structure allows the device to simultaneously achieve both fast switching and low contact resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of TFTs with low parasitic resistance, improving performance and allowing for the integration of peripheral devices like power gates and I/O transistors in the BEOL, resulting in a 5-10% density improvement for given devices, while maintaining low-temperature processing compatibility.
Implementation Method 1
combining thick Indium-Tin-Oxide (ITO) layers for metallic properties and thin ITO layers for semiconducting properties to form TFTs with low parasitic resistance
Implementation Method 2
combining thick Indium-Tin-Oxide (ITO) layers for metallic properties and thin ITO layers for semiconducting properties to form TFTs with low parasitic resistance
Implementation Method 3
depositing at least one oxide semiconductor layer over an interconnect level dielectric layer
Data Source
AI summary
A transistor, integrated semiconductor device and methods of making. The transistor includes a patterned gate electrode, a dielectric layer located over the patterned gate electrode and a patterned first oxide semiconductor layer comprising a channel region and source/drain regions located on sides of the channel region. The thickness of the source/drain regions is greater than a thickness of the channel region. The transistor also includes contacts located on the patterned first oxide semiconductor layer and connected to the source/drain regions of the patterned first oxide semiconductor layer.