Thick Top Metal Interconnect Layer for Stress Relief and Power Distribution
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Solution Overview
Problem
The integration of low-k dielectric materials in semiconductor interconnect stacks is prone to delamination due to insufficient strength and mismatched thermal expansion coefficients, leading to stress-related failures and compromised power distribution.
Innovation Solution
A thick top metal interconnect layer with a high modulus dielectric is introduced between the low-k dielectric layers and the package, acting as a stress attenuator and providing effective power distribution, while allowing for deeper trenches and wider via patterns to reduce resistive voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If low-k dielectric materials are integrated into interconnect stacks, then power distribution capability is improved, but delamination occurs due to insufficient strength and mismatched thermal expansion coefficients
Solution Approach 1:
A thick top metal interconnect layer is introduced as an intermediary stress-relief layer between the low-k dielectric layers and the package. This intermediate layer acts as a mediator that decouples the thermal expansion mismatch between the low-k dielectric and the package, preventing direct stress transmission that causes delamination while preserving power distribution capability.
Solution Approach 2:
The interconnect stack employs a composite structure combining multiple materials with different properties: low-k dielectric materials for power distribution, a thick top metal layer for stress relief, and various underlying metal layers. This composite architecture allows each material to fulfill its specific function while working together to resolve the contradiction between power distribution and delamination resistance.
2Strength
If a thick top metal interconnect layer is introduced for stress relief, then mechanical strength is enhanced and stress on critical layers is reduced, but device complexity increases
Solution Approach 1:
The thick top metal interconnect layer serves multiple functions simultaneously: it provides stress relief to prevent delamination, acts as a power distribution conduit, and offers mechanical strength enhancement. By making this single layer multi-functional, the design avoids adding separate dedicated components for each function, thereby limiting the increase in device complexity.
3Power
If deeper trenches and wider via patterns are used in the thick top metal layer, then resistive voltage drop is reduced and power delivery is improved, but manufacturing precision requirements increase
Solution Approach 1:
The design changes the geometric parameters of the top metal layer structures by creating deeper trenches and wider via patterns. These parameter modifications increase the cross-sectional area of current paths, thereby reducing resistive voltage drop and improving power delivery. The parameter changes are optimized to balance performance improvement with manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances mechanical strength, reduces stress on critical layers, improves power delivery, and allows for more interconnect layers with low-k properties, increasing feature size scaling and layout density without sacrificing performance.
Implementation Method 1
A thick top metal interconnect layer with a high modulus dielectric is introduced between the low-k dielectric layers and the package, acting as a stress attenuator
Implementation Method 2
providing effective power distribution, while allowing for deeper trenches and wider via patterns to reduce resistive voltage drop
Implementation Method 3
The integration of low-k dielectric materials in semiconductor interconnect stacks is prone to delamination due to insufficient strength and mismatched thermal expansion coefficients
Data Source
AI summary
An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.