Thick Top Metal Layer for Semiconductor Interconnection Resistance
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Solution Overview
Problem
Semiconductor devices face challenges with increased interconnection resistance and reduced signal transmission rates due to smaller sectional areas, affecting mass production efficiency and reliability.
Innovation Solution
A semiconductor device design featuring multiple interconnections and plugs with varying thicknesses and materials within insulating layers, including a thick top metal layer, to enhance current driving capability and signal transmission rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the sectional area of interconnections is reduced to increase integration density, then integration density is improved, but interconnection resistance increases and signal transmission rate decreases
Solution Approach 1:
The patent changes the thickness parameter of the metal interconnection layer, forming a thick top metal layer with thickness of 2 to 100 times that of conventional layers. This parameter change reduces interconnection resistance and improves signal transmission rate while maintaining high integration density through the selective thickening of only the top metal layer.
Solution Approach 2:
The patent applies local quality by making only the top metal layer thick while keeping other interconnection layers at conventional thickness. This localized thickening is applied specifically where high current driving capability is needed, such as in power supply lines and signal transmission lines, without increasing the overall device complexity.
2Quantity of substance
If the sectional area of interconnections is reduced to increase integration density, then integration density is improved, but signal transmission rate decreases
Solution Approach 1:
The patent changes the thickness parameter of the top metal layer to create a thick top metal layer that provides low resistance paths for signal transmission. This parameter change enables high-speed signal transmission while maintaining high integration density through the selective application of thick metal layers only where needed.
3Reliability
If a thick top metal layer is formed to reduce interconnection resistance, then interconnection resistance is reduced, but device complexity increases
Solution Approach 1:
The patent applies local quality by forming thick metal layers only in specific interconnection regions where high current density and low resistance are critical, such as power supply lines and major signal paths. Other interconnection layers maintain conventional thickness, thereby reducing overall device complexity while achieving the desired electrical performance.
Data Source
AI summary
A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.