Thickened Etch Stop Layer for Semiconductor Via Reliability
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability due to issues such as over etching during the formation of via openings, which can result in damage to the second conductive layer and reduced reliability.
Innovation Solution
A semiconductor device design featuring a second etch stop layer with greater thickness than the first etch stop layer, formed of the same material, and a method for fabricating this device that includes a via etch process using carbon and halogen-rich etchants to prevent over etching, along with a punch etch process to form through substrate vias, ensuring the integrity of both etch stop layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the second etch stop layer has greater thickness than the first etch stop layer, then over etching is compensated and reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by making the second etch stop layer have a greater thickness than the first etch stop layer. Specifically, the second etch stop layer is positioned between the second conductive layer and the bonding interface, while the first etch stop layer is positioned between the first conductive layer and the bonding interface. The increased thickness of the second etch stop layer provides localized protection against over etching during via formation processes, compensating for the specific vulnerabilities at that location without uniformly increasing the complexity of the entire device structure.
Solution Approach 2:
The patent segments the etch stop function into two separate layers (first etch stop layer and second etch stop layer) positioned at different locations within the stacked semiconductor devices. This segmentation allows each layer to serve specific protective functions during different etching operations, with the second etch stop layer providing enhanced protection against over etching during via formation in the second semiconductor die, while the first etch stop layer provides protection during via formation in the first semiconductor die.
2Reliability
If via etch process is performed to form through substrate vias, then electrical connectivity is achieved, but over etching can damage the second conductive layer
Solution Approach 1:
The patent applies beforehand cushioning by positioning the second etch stop layer between the second conductive layer and the bonding interface, with the second etch stop layer having a greater thickness than the first etch stop layer. This thicker second etch stop layer serves as a protective cushion that compensates for over etching that may occur during the via etch process, preventing the etchant from reaching and damaging the second conductive layer while still allowing electrical connectivity to be achieved through the formed vias.
Solution Approach 2:
The patent uses the second etch stop layer as an intermediary protective layer between the second conductive layer and the etching process. This intermediary layer with greater thickness mediates the interaction between the etchant and the second conductive layer, allowing the via etch process to proceed to achieve electrical connectivity while preventing the harmful effects of over etching from reaching the conductive layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased thickness of the second etch stop layer compensates for over etching, enhancing the yield and reliability of the semiconductor device by preventing complete removal and damage to the second conductive layer during the via opening formation process.
Implementation Method 1
a via etch process using carbon and halogen-rich etchants to prevent over etching
Data Source
AI summary
The present application discloses provides a method for fabricating a semiconductor device including providing a first semiconductor die including a first conductive layer, forming a first etch stop layer on the first conductive layer, bonding a second semiconductor die, which includes a second conductive layer above the first etch stop layer and a second etch stop layer on the second conductive layer, onto the first etch stop layer, performing a via etch process to concurrently form a first via opening to expose the first etch stop layer and a second via opening to expose the second etch stop layer, conformally forming isolation layers in the first via opening and the second via opening, performing a punch etch process to extend the first via opening and the second via opening, and concurrently forming a first through substrate via in the first via opening and a second through substrate via in the second via opening.