Thickened Poly Gate for High Voltage Logic Devices
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Solution Overview
Problem
As device geometries shrink, poly gates for high voltage logic devices become too thin, allowing HV LDD implant penetration into the channel region, which adversely affects performance, and lowering implant energy to prevent this limits operational voltage.
Innovation Solution
A method is developed to form memory devices with thickened conductive layers in high voltage logic device areas, preventing implant penetration by maintaining a sufficiently thick poly gate, achieved through specific layer deposition and etching processes, ensuring high voltage implantation without channel region penetration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device geometries are scaled down to smaller sizes, then productivity and integration density are improved, but the poly gate becomes too thin to effectively block the HV LDD implant
Solution Approach 1:
The patent applies local quality by forming a thicker poly gate layer specifically in the high voltage logic device area compared to other regions. This is achieved through selective deposition processes that deposit additional poly gate material over the HV LDD implant region, creating a locally enhanced gate structure that provides sufficient blocking capability for high voltage implants while maintaining standard geometry scaling benefits in other areas of the device.
2Object-affected harmful factors
If implant energy is lowered to prevent poly layer penetration, then the harmful effect of channel region implantation is reduced, but the gated-diode breakdown voltage decreases
Solution Approach 1:
The patent applies preliminary anti-action by pre-forming a thicker poly gate layer before performing the high voltage LDD implant. This enhanced gate structure is created in advance to specifically counteract and prevent the harmful penetration of implant ions into the channel region. By establishing this protective barrier beforehand, the patent enables the use of higher implant energies necessary for achieving adequate gated-diode breakdown voltage without suffering from channel region contamination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents implant penetration into the channel region, allowing for high voltage logic device fabrication without performance degradation, while maintaining operational voltage capabilities.
Implementation Method 1
performing a conductive material deposition to thicken the first conductive layer in the memory area and the HV area
Implementation Method 2
performing an HV LDD implant to form source/drain regions in the HV area
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~1F
AI summary
A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.