Thickened Redistribution Layer Semiconductor Package
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving smaller footprint, higher density, and efficient electrical interconnection, particularly in forming thick redistribution layers (RDLs) for semiconductor devices, which are essential for miniaturization and performance enhancement.
Innovation Solution
A method involving the formation of thick RDL traces over semiconductor die, which are then encapsulated with a non-photoimagable material and exposed using laser ablation or grinding, allowing for the creation of fan-in or fan-out interconnect structures and electrical connections, enabling efficient packaging and reduced package warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional thin RDL structures are used, then manufacturing process is simpler, but electrical interconnectivity and current carrying capacity are insufficient
Solution Approach 1:
The patent changes the thickness parameter of the RDL from traditional thin structures to thick structures (e.g., 10-50 micrometers), which fundamentally improves electrical interconnectivity and current carrying capacity while enabling new packaging architectures
Solution Approach 2:
The patent transitions from planar thin RDLs to three-dimensional thick RDLs with vertical height, enabling fan-in and fan-out interconnect configurations that provide additional spatial dimensions for routing and connection
2Reliability
If thick RDL traces are formed, then electrical interconnectivity and current capacity improve, but manufacturing complexity increases
Solution Approach 1:
The patent forms thick RDL traces and other package structures on a carrier substrate before mounting the semiconductor die, allowing preliminary preparation and integration of multiple functions in advance of final assembly
Solution Approach 2:
The patent combines multiple manufacturing functions into integrated processes, such as forming thick RDLs that simultaneously serve as electrical interconnects and structural elements, and integrating encapsulation with interconnect formation in unified process steps
3Productivity
If multiple packaging processes are performed separately, then process control is easier, but production time and cost increase
Solution Approach 1:
The patent merges multiple separate packaging processes into integrated wafer-level operations, including simultaneous formation of thick RDLs, die mounting, encapsulation, and interconnect creation in unified process flows that operate on entire wafers rather than individual devices
Solution Approach 2:
The patent performs preliminary preparation of all package structures, interconnects, and encapsulation materials on carrier substrates before die mounting, enabling subsequent rapid assembly and reducing overall production time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the production of semiconductor packages with enhanced electrical interconnectivity and reduced warpage, facilitating smaller device sizes, higher performance, and cost-effective manufacturing by integrating multiple processes into a single step, potentially replacing traditional packaging technologies like QFN and FBGA.
Implementation Method 1
exposed using laser ablation or grinding
Implementation Method 2
exposed using laser ablation or grinding
Data Source
AI summary
A method of making a semiconductor package can comprise forming a plurality of thick redistribution layer (RDL) traces over active surfaces of a plurality of semiconductor die that are electrically connected to contact pads on the plurality of semiconductor die, singulating the plurality of semiconductor die comprising the plurality of thick RDL traces, mounting the singulated plurality of semiconductor die over a temporary carrier with the active surfaces of the plurality of semiconductor die oriented away from the temporary carrier, disposing encapsulant material over the active surfaces and at least four side surfaces of each of the plurality of semiconductor die, over the plurality of thick RDL traces, and over the temporary carrier, forming a via through the encapsulant material to expose at least one of the plurality of thickened RDL traces with respect to the encapsulant material, removing the temporary carrier, and singulating the plurality of semiconductor die.