Thin-Body 3D Memory Cell Layout for Higher Density Refresh Stability
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Solution Overview
Problem
The integration degree of two-dimensional semiconductor memory devices is limited by the high cost and complexity of pattern refinement techniques, necessitating the development of three-dimensional semiconductor memory devices with vertically stacked memory cells to enhance integration density.
Innovation Solution
A semiconductor memory device with a substrate, vertically oriented bit lines, laterally positioned active layers, and word lines where the active layer includes a thin-body channel, thinner than the word lines, improving memory cell density and reducing parasite capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use conventional active layer thickness, then manufacturing is easier, but memory cell density and integration degree are limited
Solution Approach 1:
The patent transitions from two-dimensional to three-dimensional memory cell arrangement by vertically stacking multiple memory cells. The active layer is positioned at different heights (first active layer at first height, second active layer at second height), enabling vertical integration and significantly increasing memory cell density without requiring further refinement of two-dimensional patterning processes.
2Reliability
If active layer thickness is increased to improve manufacturing ease, then device fabrication is simpler, but floating body effect and refresh characteristics deteriorate
Solution Approach 1:
The patent specifies a particular thickness range for the active layer (5nm to 20nm) to optimize the balance between manufacturability and device performance. This thin-body channel thickness is sufficient to suppress the floating body effect and improve refresh characteristics while remaining compatible with existing semiconductor fabrication capabilities.
3Quantity of substance
If three-dimensional vertically stacked memory cells are implemented, then memory cell density increases, but device structure and manufacturing process complexity increase
Solution Approach 1:
The patent divides the memory device into multiple independent but identical memory cell units stacked vertically. Each memory cell contains a complete set of components (bit line, active layer, word lines, capacitor) that can be independently formed and function autonomously. This modular segmentation allows complex 3D integration to be achieved through repeated stacking of standardized units.
Solution Approach 2:
The patent employs a universal bit line structure that serves multiple functions: it is shared by multiple memory cells at different heights, acts as both source and drain for different cells, and enables vertical current flow paths. This multi-functional design reduces the total number of required components and simplifies the overall device architecture despite the three-dimensional configuration.
Data Source
AI summary
The present invention provides a highly integrated memory cell and a semiconductor memory device including the same. According to the present invention, a semiconductor memory device comprises: a substrate; an active layer spaced apart from the substrate, extending in a direction parallel to the substrate, and including a thin-body channel; a bit line extending in a direction vertical to the substrate and connected to one side of the active layer; a capacitor connected to another side of the active layer; and a first word line and a second word line extending in a direction crossing the thin-body channel with the thin-body channel interposed therebetween, wherein a thickness of the thin-body channel is smaller than thicknesses of the first word line and the second word line.