Thin Bottom Nanosheet Channel Layout for Leakage Control
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Solution Overview
Problem
The scaling down of semiconductor devices leads to increased complexity and challenges such as short-channel effects and parasitic capacitance, which compromise the control of current flow and induce leakage concerns.
Innovation Solution
A semiconductor device with a thin bottom channel and a gate structure that encircles the channel layer, featuring a dielectric spacer between the bottom channel and the substrate, which eliminates parasitic capacitance and reduces current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the semiconductor device is scaled down to increase functional density, then production efficiency is improved and costs are lowered, but short-channel effects and parasitic capacitance increase, compromising current flow control and increasing leakage
Solution Approach 1:
The gate structure transitions from a planar configuration to a three-dimensional wraparound structure that encircles the channel layer. This dimensional change allows the gate to control current flow from multiple directions, significantly improving control effectiveness despite device scaling, while the thin bottom channel dimension reduces parasitic capacitance
2Reliability
If the gate structure is designed to encircle the channel layer to improve current flow control, then short-channel effects are reduced, but device complexity increases
Solution Approach 1:
The channel layer is segmented into multiple thin layers stacked vertically, with the gate structure wrapping around each layer. This segmentation allows the complex three-dimensional gate structure to be constructed from simpler repeated units, making the manufacturing process more manageable while achieving superior current flow control through the wraparound configuration
3Reliability
If a thin bottom channel is used to reduce parasitic capacitance, then leakage is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The channel layer thickness is changed to an ultra-thin dimension (few nanometers), which fundamentally alters the electrical characteristics by reducing parasitic capacitance and preventing leakage paths. This parameter change requires precise control during manufacturing, but the thin dimension itself becomes the key to achieving reliable device operation at scaled sizes
Data Source
AI summary
A semiconductor device includes semiconductor nanosheets, a gate structure, and a dielectric spacer. The semiconductor nanosheets are vertically stacked over each other, disposed above a semiconductor substrate, and serve as channel regions. A bottommost semiconductor nanosheet most proximate from the semiconductor substrate is a thinnest nanosheet of the semiconductor nanosheets. The gate structure surrounds each of the semiconductor nanosheets in a first cross-section, and the dielectric spacer is interposed between the bottommost semiconductor nanosheet and the semiconductor substrate and adjoins the gate structure in the first cross-section.