Thin Fan-Out Multi-Chip Stacked Package Structure
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Solution Overview
Problem
The existing multi-chip stack package structure faces challenges in reducing thickness due to the requirement of substrate thickness and wiring arc height, leading to issues like wire sweep during encapsulation, which affects manufacturing precision and yield.
Innovation Solution
A thin fan-out multi-chip stacked package structure is developed, incorporating a chip stack, dummy spacer, alignment structure, bonding wires, encapsulant, and redistribution layer, which allows for a ultra-thin package design by eliminating the need for substrate thickness and enhancing manufacturing precision through the use of a redistribution layer with fan-out circuits and passivation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If conventional multi-chip stack package structure is used with substrate and arc-shaped wiring, then electrical connection between chips and substrate is achieved, but the total thickness of the package structure cannot be reduced due to substrate thickness and wiring arc height requirements
Solution Approach 1:
The patent removes the substrate from the conventional package structure, replacing it with a chip stack directly mounted on a support structure. This extraction of the substrate eliminates the need for arc-shaped wiring and allows vertical wire segments to be used instead, directly reducing the package thickness while maintaining electrical connection functionality
Solution Approach 2:
The patent transitions from horizontal arc-shaped wiring on a substrate to vertical wire segments extending upward from the chip stack. This dimensional change from planar to vertical wiring enables the package thickness to be reduced to nearly the chip stack height, as the wiring no longer requires the horizontal space needed for arcs
2Reliability
If long bonding wires are used in conventional package structure, then electrical connection is achieved, but wire sweep causing short-circuit occurs easily during encapsulant formation
Solution Approach 1:
Instead of using long horizontal bonding wires that sweep during encapsulation, the patent inverts the wiring approach by using short vertical wire segments that extend upward from the chip stack. This inversion eliminates the sweeping motion during encapsulant formation, preventing short-circuits while maintaining electrical connectivity
Solution Approach 2:
The patent changes the wiring geometry from horizontal arcs to vertical segments, fundamentally altering the spatial parameters of the bonding wires. This parameter change from horizontal to vertical orientation eliminates the wire sweep issue during encapsulation while reducing the required wire length
3Manufacturing precision
If conventional packaging process is used without alignment structure, then manufacturing is simpler, but precision during manufacturing process is reduced
Solution Approach 1:
The patent introduces an alignment structure as an intermediary element between the chip stack and the support structure. This alignment structure provides reference features that enable precise positioning and alignment during the packaging process, improving manufacturing precision without significantly increasing overall complexity
Solution Approach 2:
The alignment structure is prepared in advance on the support structure before chip stack mounting. This preliminary preparation of alignment features enables precise positioning to be performed during assembly, improving manufacturing precision while keeping the process organized and manageable
Data Source
AI summary
A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.