Thin-Film Transistor Array Layout for Higher Pixel Integration
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Solution Overview
Problem
Existing thin film transistor arrays face challenges in achieving a high degree of integration of pixel circuits, which affects the resolution and display quality of display devices.
Innovation Solution
The thin film transistor array is designed with a specific arrangement of transistors, including data write, driving, compensation, emission control, and initialization transistors, connected in a manner that allows for improved integration by sharing transistors between adjacent pixel circuits, and the use of connection lines on the same layer as gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are shared between adjacent pixel circuits, then the degree of integration is improved, but the manufacturing complexity increases
Solution Approach 1:
Adjacent pixel circuits share common transistors (data write transistors, driving transistors, compensation transistors, emission control transistors, and initialization transistors) to reduce the total number of transistors required. This merging approach increases the degree of integration by allowing fewer transistors to serve multiple pixel circuits simultaneously.
Solution Approach 2:
The pixel circuit array is divided into adjacent groups that can share transistors. By segmenting the overall circuit design into modular units with shared components, the patent achieves higher integration while maintaining manageable manufacturing complexity through systematic sharing patterns.
2Productivity
If transistors are arranged in a specific configuration for sharing, then the integration is improved, but the layout complexity increases
Solution Approach 1:
Transistors are positioned at boundaries between adjacent pixel circuits so they can be shared. The data write transistor, driving transistor, compensation transistor, emission control transistor, and initialization transistor are strategically placed to serve multiple pixel circuits, reducing the total transistor count while maintaining functional integrity.
Solution Approach 2:
Each shared transistor is designed to perform multiple functions across different pixel circuits. The same transistor serves as a data write transistor for one pixel circuit and as a driving transistor for another, making the component universal and reducing overall layout complexity despite the advanced sharing arrangement.
3Ease of manufacture
If connection lines are placed on the same layer as gate lines, then manufacturing is simplified, but the routing options are reduced
Solution Approach 1:
Connection lines for shared transistors are routed on the same layer as gate lines, combining the routing functions into a single layer. This approach simplifies manufacturing by reducing the number of layers that need to be processed separately while maintaining electrical connectivity through the shared transistor structures.
Solution Approach 2:
The shared transistors act as intermediaries that enable connection lines to be routed on the same layer as gate lines. These transistors provide the necessary electrical pathways, allowing connection lines to share the routing layer without creating conflicts, thus simplifying manufacturing while managing routing complexity through the intermediary transistor structures.
Data Source
AI summary
A thin film transistor array includes a first gate line extending in a first direction, first and second data lines each extending in a second direction, a first write transistor connected to the first gate line and the first data line, a second write transistor connected to the first gate line and the second data line and arranged in the first direction from the first write transistor, a first driving transistor connected to the first write transistor and arranged in the second direction from the first write transistor, a second driving transistor connected to the second write transistor, arranged in the first direction from the first driving transistor, and arranged in the second direction from the second write transistor, and a first operation control transistor connected to the first driving transistor and the second driving transistor and arranged in the second direction from the first driving transistor.