Thin-Film Decoupling Capacitor Manufacturing on Wiring Substrates
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Solution Overview
Problem
Existing methods for manufacturing decoupling capacitors and wiring substrates face limitations in producing thinner and smaller components, which restrict their integration with semiconductor chips due to constraints in manufacturing thinner decoupling capacitors and wiring substrates.
Innovation Solution
A method involving the formation of a peeling layer on a base, followed by multiple layers of a capacitor with specific electrode and dielectric materials, and the creation of via holes for wiring connections, allowing for the separation of the base from the capacitor layers to achieve a thinner structure while maintaining electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a decoupling capacitor is mounted on the rear side of the wiring substrate or buried in the substrate, then the capacitor can be integrated with the semiconductor chip, but the thickness and size of the wiring substrate cannot be reduced further
Solution Approach 1:
The capacitor structure is segmented into multiple thin layers (first electrode layer, dielectric layer, second electrode layer) that can be formed sequentially. This segmentation allows each layer to be manufactured with standard thin-film techniques, enabling the overall capacitor to achieve reduced thickness while maintaining manufacturability.
Solution Approach 2:
The invention transitions from mounting capacitors on the rear side or burying them in the substrate to forming them as thin-film structures directly on the front surface of the wiring substrate. This dimensional change allows the capacitor to be integrated in the same plane as the semiconductor chip, reducing the overall thickness without compromising manufacturability.
2Reliability
If the decoupling capacitor is positioned near the semiconductor chip, then the inductance of the connection is reduced, but the manufacturing complexity increases
Solution Approach 1:
The capacitor manufacturing process is merged with the existing wiring substrate fabrication process. The first electrode layer, dielectric layer, and second electrode layer are formed using the same thin-film deposition and patterning equipment already present in the manufacturing line, thereby reducing overall manufacturing complexity while achieving low inductance through close positioning.
Solution Approach 2:
The multilayer thin-film structure serves multiple functions: it provides the decoupling capacitance function, acts as part of the wiring substrate structure, and can be integrated with existing semiconductor packaging processes. This multi-functionality reduces the need for separate manufacturing steps, thereby reducing complexity while maintaining reliability.
Data Source
AI summary
The present invention discloses a method of manufacturing a wiring substrate to which a semiconductor chip mounted. The method includes the steps of forming a base, forming a peeling layer on the base, forming a capacitor having a plurality of layers on the peeling layer, and forming a wiring part in the capacitor for connecting the capacitor to the semiconductor chip.