Thin-Film Fin Transistor Structure With Spacer-Defined Fin Width
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Solution Overview
Problem
Conventional methods for fabricating fins in integrated circuits lack control over fin width, leading to variations in height and width across individual fins and multiple fins on a wafer, which affects transistor performance.
Innovation Solution
The method involves forming fins from a sidewall of channel material after a spacer etch, using atomic layer deposition or chemical vapor deposition to control the width of the fins, allowing for more precise control over fin dimensions and reducing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to fabricate fins, then the fabrication process is simple, but the control over fin width is poor leading to variations in height and width across fins
Solution Approach 1:
A spacer layer is introduced as an intermediary material between the mandrel and the final fin structure. The spacer layer serves as a mediator that transfers the precise dimensional control from the deposition process to the fin width, enabling accurate fin width control without directly etching the mandrel to the final fin dimensions
Solution Approach 2:
The spacer layer is deposited in advance before the final fin formation step. This preliminary deposition establishes the exact fin width dimensions beforehand, allowing subsequent processing steps to simply transfer this pre-determined width to the final fin structure, thereby improving manufacturing precision
2Manufacturing precision
If conventional fin fabrication methods are used, then the process steps are fewer, but variations in fin height and width across individual fins and multiple fins on a wafer occur
Solution Approach 1:
The spacer layer performs multiple functions automatically: it defines fin width through conformal deposition, serves as an etch stop layer to prevent over-etching, and provides a template for fin formation. This self-service approach ensures consistent fin dimensions across the wafer without requiring additional separate process steps for each function
Solution Approach 2:
The invention changes the critical parameter from etch selectivity to deposition conformality. By controlling the deposition thickness and uniformity of the spacer layer, precise fin width control is achieved across all fins on the wafer, reducing dimensional variations while maintaining fabrication efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables significant reduction in width and height variations across fins, improving the consistency and performance of thin film transistors by allowing for precise control over fin dimensions.
Implementation Method 1
conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate
Implementation Method 2
using atomic layer deposition or chemical vapor deposition to control the width of the fins
Data Source
AI summary
Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed.