Thin-Film IC Redistribution Layer Using Mixed Patterning Techniques
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Solution Overview
Problem
The complexity and cost of manufacturing thin-film integrated circuits (ICs) are high due to the use of single, high-precision patterning techniques like photolithography, which increases process duration and generates waste.
Innovation Solution
A method is proposed that combines different fabrication techniques for patterning and deposition in the manufacture of thin-film ICs, allowing for the use of lower precision techniques for features that do not require high precision, thereby reducing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic patterning is used for all features, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies different patterning techniques to different regions of the IC based on local precision requirements. High-precision photolithography is used only for critical features requiring small minimum feature sizes, while lower-precision techniques are used for non-critical features, thereby reducing overall process complexity while maintaining necessary precision where required.
Solution Approach 2:
The fabrication process is segmented into different stages with different patterning techniques. The first fabrication technique (photolithographic) handles critical high-precision layers, while the second fabrication technique handles less critical layers, allowing each segment to be optimized independently for its specific precision requirements.
2Manufacturing precision
If photolithographic patterning is used for all features, then manufacturing precision is improved, but manufacturing duration increases
Solution Approach 1:
The patent applies different patterning techniques to different regions of the IC based on local precision requirements. High-precision photolithography is used only for critical features requiring small minimum feature sizes, while lower-precision techniques are used for non-critical features, thereby reducing overall process complexity while maintaining necessary precision where required.
Solution Approach 2:
The fabrication process is segmented into different stages with different patterning techniques. The first fabrication technique (photolithographic) handles critical high-precision layers, while the second fabrication technique handles less critical layers, allowing each segment to be optimized independently for its specific precision requirements.
3Manufacturing precision
If photolithographic patterning is used for all features, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent applies different patterning techniques to different regions of the IC based on local precision requirements. High-precision photolithography is used only for critical features requiring small minimum feature sizes, while lower-precision techniques are used for non-critical features, thereby reducing overall process complexity while maintaining necessary precision where required.
Solution Approach 2:
The fabrication process is segmented into different stages with different patterning techniques. The first fabrication technique (photolithographic) handles critical high-precision layers, while the second fabrication technique handles less critical layers, allowing each segment to be optimized independently for its specific precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity, duration, and cost of manufacturing thin-film ICs while maintaining functionality and reliability by leveraging the benefits of various patterning techniques and avoiding their disadvantages.
Implementation Method 1
forming, using a second fabrication technique, a conductive layer on the plurality of electronic components to form a redistribution layer, RDL
Implementation Method 2
the second fabrication technique includes laser ablation
Data Source
AI summary
A method for fabricating a thin-film integrated circuit, IC, including a plurality of electronic components, the method comprising: forming, using a first fabrication technique, the plurality of electronic components, and forming, using a second fabrication technique, a conductive layer on the plurality of electronic components to form a redistribution layer, RDL, wherein the first fabrication technique includes photolithographic patterning, and the first fabrication technique is different to the second fabrication technique.


