Thin-Film IC Tile Packaging with Ground Vias for Microwave Testing
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Solution Overview
Problem
Conventional silicon-based integrated circuit (IC) packaging methods, such as wire-bonding and flip-chip packaging, face challenges in providing effective grounding and testing at microwave frequencies due to parasitic inductance and capacitance issues, limiting their use in high-frequency applications and requiring specialized handling and equipment.
Innovation Solution
The development of a flip-chip assembly process where IC dies are fabricated with solder bumps or copper pillars and assembled onto a thin-film tile with patterned vias and ground planes, allowing for close proximity ground connections and automated testing before being singulated into die/tile assemblies, which can be packaged conventionally or used directly by customers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If wire-bonding or flip-chip packaging is used for silicon-based ICs, then the ICs can be packaged and handled easily, but parasitic inductance and capacitance degrade microwave performance at high frequencies
Solution Approach 1:
The patent transitions from planar wire-bonding to three-dimensional vertical vias that penetrate through the substrate thickness, creating direct ground connections from top surface to bottom surface. This dimensional change reduces ground inductance by eliminating long lateral wire paths and enables effective microwave frequency operation while maintaining packaged form factor.
Solution Approach 2:
The patent incorporates ground vias and grounding structures during the substrate fabrication process before IC mounting, rather than adding them afterward. This preliminary action ensures optimal ground connections are already in place, reducing parasitic effects from the start and enabling reliable microwave performance in the final packaged product.
2Reliability
If through-hole vias are used in III-V semiconductor substrates, then low inductance ground connections are achieved, but material cost and toxicity increase
Solution Approach 1:
The patent changes the substrate material parameter from III-V semiconductors (GaAs, InP) to silicon-based materials, maintaining the through-via grounding architecture. This parameter change achieves similar low-inductance ground connections while using abundant, non-toxic, and lower-cost silicon materials that are compatible with existing semiconductor manufacturing infrastructure.
Solution Approach 2:
The patent uses standard silicon substrates with conventional via fabrication processes instead of expensive III-V materials, making the grounding structure economically viable for mass production while achieving equivalent electrical performance through optimized via design and placement.
3Ease of manufacture
If silicon-based ICs without through-hole vias are used, then manufacturing cost is reduced, but automated wafer-probe testing capability is lost
Solution Approach 1:
The patent segments the substrate into multiple functional layers with dedicated via regions, allowing separate optimization of grounding, signaling, and testing functions. This segmentation enables automated wafer-probe testing through specially designed via access points while maintaining cost-effective silicon-based manufacturing throughout the substrate structure.
Data Source
AI summary
An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped or the like, and singulated. The singulated dies, which may be of different sizes and functionality, are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Sets of dies of different functionality may be tested as a system or subsystem. Once test probing is complete, the dies (or sets of dies) and tile are singulated into die/tile assemblies.