Thin-Film Interconnect Structure for IC Packaging

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Solution Overview

Problem

The semiconductor industry faces shortages and supply chain limitations due to the high demand for semiconductors, limited foundries, and constraints in redistributing layer (RDL) fanouts and organic substrates, leading to increased costs, reliability issues, and dependency on specific foundries for integrated circuit packaging.

Innovation Solution

A thin-film interconnect structure composed of polymeric layers with conductive plating is used to achieve fine pitch geometries for fanout-style redistribution of inputs/outputs, allowing for off-site fabrication and assembly, reducing substrate layers, and integrating components like capacitors or power management elements, thereby decoupling from conventional silicon-wafer approaches and improving electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional silicon-wafer approaches with organic substrates are used, then substrate layers and complexity increase, but electrical performance and signal integrity deteriorate

Engineering Contradiction:
Improvesignal integrityVSAvoidsubstrate layers
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the interconnect function from the conventional organic substrate and creates a separate thin-film interconnect structure. This structure includes multiple polymeric layers with conductive traces that can be fabricated independently and then integrated with the substrate, thereby reducing substrate complexity while maintaining signal integrity through optimized interconnect design

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the interconnect structure into multiple thin polymeric layers, each potentially serving different functions (signal routing, power distribution, etc.). This segmentation allows for independent optimization of each layer's electrical characteristics, improving overall signal integrity while distributing the complexity across manageable layers rather than requiring a monolithic complex substrate

Inventive Principle:
Principle #1Segmentation

2Reliability

If RDL fanouts and organic substrates are manufactured through limited foundries, then supply chain dependency increases, but manufacturing precision and reliability suffer

Engineering Contradiction:
Improvemanufacturing reliabilityVSAvoidsupplier flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent segments the manufacturing process into independent modules: the thin-film interconnect structure can be fabricated by one supplier using polymeric layer deposition techniques, while the substrate and die assembly can be produced by another supplier. This segmentation enables multi-vendor manufacturing, reducing supply chain dependency and improving reliability through diversified sourcing

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The thin-film interconnect structure serves as a universal interface layer that can be integrated with different substrate types and die configurations. This universality allows multiple suppliers to produce compatible components that can be assembled together, enhancing supplier flexibility while maintaining manufacturing reliability through standardized integration protocols

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If fine pitch geometries are achieved through conventional methods, then substrate complexity and cost increase, but electrical performance improves

Engineering Contradiction:
Improveelectrical performanceVSAvoidinterconnect structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs thin polymeric films as the substrate for the interconnect structure. These thin films enable the fabrication of fine pitch geometries with reduced parasitic effects compared to conventional thick organic substrates. The thin-film nature allows for better control of electrical characteristics while achieving fine pitch routing, improving electrical performance without proportionally increasing complexity

Inventive Principle:
Principle #30Flexible shells and thin films

Solution Approach 2:

The patent uses composite structures combining polymeric layers with conductive materials (such as copper traces or plated through-holes) to achieve fine pitch geometries. The polymeric material provides mechanical support and insulation, while the conductive elements provide the fine pitch interconnect paths. This composite approach enables high-density routing with controlled electrical characteristics without requiring the entire substrate to be complex

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables more resilient and cost-effective semiconductor architecture by allowing interconnect structures to be fabricated off-site, reducing substrate layers, improving electrical performance, and enhancing signal integrity, while enabling the use of different suppliers for building blocks, thus addressing manufacturability and multi-vendor constraints.

Implementation Method 1

A thin-film interconnect structure that includes one or more polymeric layers and conductive plating

Methodology Applied
Scientific EffectConductive plating: Electroplating

Data Source

PatentUS20230075607A1Architecture and packaging for integrated circuits
Publication Date: 2023.03.09 CISCO TECHNOLOGY INC
  • US20230075607A1 patent drawing
  • US20230075607A1 patent drawing
  • US20230075607A1 patent drawing

AI summary

An apparatus is provided that includes a thin-film interconnect structure that comprises one or more polymeric layers and conductive plating, a first surface of the thin-film interconnect structure being configured to receive one or more dies, and a second surface of the thin-film interconnect structure being configured to receive a substrate. A method of assembling the apparatus into an integrated circuit assembly is also provided.