Multi-Port Thin-Film Memory Cell Isolation for Concurrent Read-Write
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Solution Overview
Problem
Dual-port SRAM devices face interference between read and write operations, leading to a characteristic drop in semiconductor memory cell performance due to simultaneous execution of these operations.
Innovation Solution
A semiconductor storage device with an isolation circuit that prevents the second access circuit from altering the data state during read operations, allowing for concurrent read and write operations without disturbing the stored data, and a method for programming memory cells using a storage node coupled to an access device and an isolation circuit with an output node to determine when the data state is altered.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dual port SRAM is configured with additional active transistors to perform read and write operations simultaneously, then operation speed is improved, but read and write operations interfere with each other causing characteristic drop in memory cell performance
Solution Approach 1:
The memory cell is segmented into distinct read and write circuits with separate access paths. The read circuit uses read access transistors (RN1, RN2) connected to read bit lines (BLR, !BLR), while the write circuit uses write access transistors (WN1, WN2) connected to write bit lines (BLW, !BLW). This segmentation allows independent operation of read and write functions without mutual interference, resolving the contradiction between speed and reliability.
Solution Approach 2:
Isolation transistors (IN1, IN2) are introduced as intermediary elements between the read circuit and the storage latch. These isolation transistors act as mediators that prevent read operations from directly affecting the write path and vice versa. The isolation transistors are controlled by isolation word lines (IWL) to enable or disable the isolation path, thereby protecting the memory cell from interference while maintaining high-speed concurrent operations.
2Productivity
If read and write operations are performed simultaneously in dual port SRAM, then productivity is improved, but interference between operations causes characteristic drop
Solution Approach 1:
The access circuits are segmented into independent read and write paths with separate bit lines and access transistors. This allows simultaneous read and write operations to proceed independently without interfering with each other, maintaining both productivity and data integrity.
Solution Approach 2:
Isolation transistors controlled by isolation word lines serve as intermediaries that prevent unwanted coupling between read and write operations. When isolation is enabled, these transistors block potential interference paths, ensuring data integrity while allowing concurrent operations to maintain high productivity.
3Ease of operation
If multiple access devices provide multiple access paths to read and write latch data, then ease of operation is improved, but complexity of the memory cell increases
Solution Approach 1:
The memory cell design uses universal latch structures that can be accessed through multiple independent paths. The same latch (Q, !Q) serves as the storage element for both read and write operations, while the access transistors and bit lines provide multi-functional access capability. This universality allows ease of operation without proportionally increasing complexity.
Solution Approach 2:
The access paths are segmented into distinct read and write circuits, each with dedicated transistors and bit lines. This segmentation provides clear functional separation that simplifies control logic and operation, making the multi-access capability easier to use while managing complexity through organized structure.
Data Source
AI summary
In a first aspect, a semiconductor storage device, comprising: a metal line coupled to a gate of an access transistor, wherein the gate material is deposited substantially above the metal line. In a second aspect, a semiconductor storage device, comprising: a first port to write data to a storage element; and a second port to read a signal generated by the storage element; and a first metal line coupled to a gate of an access transistor coupled to the first port; and a second metal line coupled to a gate of an access transistor coupled to the second port; wherein, the gates of said access transistors are formed on a gate material deposited substantially above the metal of first and second metal lines.