Thin-Film RAM Cell Layout Using Vertical Transistor Stacking
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Solution Overview
Problem
Existing memory devices face limitations in density, vertical extension, and access line arrangement due to the implementation of transistors across a substrate.
Innovation Solution
The use of thin film transistors or vertical transistors formed above a substrate, which allows for increased memory cell density, vertical extension of transistor structures, and improved design flexibility for interconnecting memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are implemented across a substrate, then device area is reduced, but memory cell density and vertical extension are limited
Solution Approach 1:
The patent transitions from planar transistor implementation across a substrate to vertical transistor stacking above the substrate. This dimensional change from 2D to 3D architecture enables increased memory cell density by utilizing the vertical dimension, allowing multiple transistor layers to be stacked above each substrate location rather than spreading transistors horizontally across the substrate surface.
2Quantity of substance
If vertical transistors are used, then memory cell density increases, but manufacturing complexity increases
Solution Approach 1:
The vertical transistor structure is segmented into distinct functional layers including gate electrodes, channel regions, and source/drain regions stacked in the vertical dimension. This segmentation allows each layer to be formed using specialized deposition and etching processes optimized for that particular structure, making the complex vertical architecture manufacturable through modular process steps rather than requiring monolithic fabrication.
3Adaptability or versatility
If substrate-based transistors are implemented, then manufacturing is simpler, but access line arrangement flexibility is reduced
Solution Approach 1:
By stacking transistors vertically above the substrate, the patent creates additional vertical routing paths for access lines. This enables more flexible interconnection designs where bit lines and word lines can be routed through multiple vertical levels, allowing improved access patterns and reduced interference between adjacent memory cells compared to planar arrangements where all connections must occur in the same horizontal plane.
Data Source
AI summary
Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.