Thin-Film Chip Resistor-Capacitor With Stacked Capacitor Layers
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Solution Overview
Problem
Conventional resistor-capacitor elements face challenges in achieving high resistance and capacitance while maintaining circuit miniaturization, and the low-temperature ceramic cofiring process is prone to poor production quality due to thermophysical property issues.
Innovation Solution
A thin-film chip resistor-capacitor design with a resistor layer and additional thin-film capacitor layers coupled by terminal electrodes, featuring comb-shaped capacitor electrodes and dielectric layers to enhance capacitance without sacrificing resistance, and a method of fabrication involving deposition and patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size and design area of the resistor and capacitor are reduced to achieve circuit miniaturization, then the device size is reduced, but the resistance and capacitance values decrease and power dissipation performance deteriorates
Solution Approach 1:
The patent transitions from planar 2D electrode arrangements to a 3D vertical stacked architecture. Multiple capacitor layers are stacked above the resistor layer, utilizing the vertical dimension to increase capacitance without expanding the device footprint. This dimensional transition allows high capacitance values to be achieved within a miniaturized device volume.
Solution Approach 2:
The patent implements a nested structure where thin-film capacitor layers are stacked within and above the resistor layer structure. The capacitor electrodes are positioned between and around the resistor traces, creating a nested arrangement that maximizes the use of available space. This nesting allows multiple functional elements to coexist in a compact volume while maintaining their individual performance characteristics.
2Ease of manufacture
If conventional low-temperature ceramic cofiring process is used to form resistor-capacitor elements, then the manufacturing process is simplified, but production quality deteriorates due to thermophysical property mismatches
Solution Approach 1:
The patent divides the resistor-capacitor element into distinct functional layers: a resistor layer and separate thin-film capacitor layers. This segmentation allows each layer to be optimized independently for its specific function, avoiding the thermophysical property conflicts that arise in cofired ceramic structures. The separate layering enables independent fabrication and optimization of resistance and capacitance characteristics.
Solution Approach 2:
The patent employs composite material structures with different layers made from materials optimized for their specific functions. The resistor layer uses materials with appropriate resistivity characteristics, while the capacitor layers use dielectric materials with high permittivity. This composite approach allows each material to contribute its optimal properties without being compromised by the requirements of other materials, thereby improving overall device performance and manufacturing quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves chip thinning and miniaturization with improved resistance and capacitance, while ensuring high heat dissipation performance and robust production quality.
Implementation Method 1
The first thin-film capacitor layer is disposed on the first dielectric layer, and has a first capacitor electrode and second capacitor electrode that are physically separated with respect to each other
Implementation Method 2
The first terminal electrode is disposed on a first side edge of the substrate, and is coupled to the resistor layer and the first capacitor electrode. The second terminal electrode is disposed on a second side edge of the substrate opposite to the first side edge, and is coupled to the resistor layer and the second capacitor electrode
Data Source
AI summary
A thin-film chip resistor-capacitor includes a substrate, a resistor layer, a dielectric layer, a thin-film capacitor layer, a first terminal electrode and a second terminal electrode. The resistor layer is disposed on the substrate. The dielectric layer is disposed on the resistor layer. The thin-film capacitor layer is disposed on the dielectric layer and includes first and second capacitor electrodes that are physically separated with respect to each other. The first terminal electrode is disposed on a first side edge of the substrate and is coupled to the resistor layer and the first capacitor electrode. The second terminal electrode is disposed on a second side edge of the substrate opposite to the first side edge and is coupled to the resistor layer and the second capacitor electrode.