Thin-Film Transistor Active Layer with Crystalline-Amorphous Regions
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Solution Overview
Problem
Current oxide semiconductor thin film transistors face challenges in manufacturing complexity and cost, with potential damage to the active layer affecting device stability and lifespan, while existing technologies struggle to balance crystalline and amorphous structures for optimal performance.
Innovation Solution
A thin film transistor design incorporating both crystalline and amorphous portions in the active layer, achieved by doping a crystalline oxide semiconductor layer with a dopant to create amorphous regions, which improves stability and reliability, and a method for manufacturing this structure involving selective doping and heat treatment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a crystalline oxide semiconductor layer is used to achieve high mobility and electrical characteristics, then the manufacturing process becomes complex and costly, but device performance is improved
Solution Approach 1:
The patent applies local quality by creating distinct crystalline and amorphous regions within the active layer. The crystalline channel portion provides high mobility and electrical characteristics, while the amorphous connection portions simplify manufacturing and reduce costs. This spatial differentiation of material properties resolves the contradiction between performance and manufacturing complexity.
Solution Approach 2:
The patent uses composite materials by combining crystalline oxide semiconductor and amorphous oxide semiconductor in a single active layer structure. The crystalline portion (e.g., cubic Bixbyite structure) delivers superior electrical properties, while the amorphous portion reduces manufacturing complexity. This composite approach allows simultaneous achievement of high performance and simplified production.
2Reliability
If dopant is doped into the active layer to improve electrical characteristics, then the active layer may be damaged and device lifespan may be impaired, but electrical performance is enhanced
Solution Approach 1:
The patent applies local quality by restricting dopant doping to specific connection portions of the active layer while keeping the channel portion undoped or lightly doped. This localized doping approach enhances electrical characteristics in regions where high conductivity is needed (connection portions) without exposing the entire active layer to doping-induced damage, thereby preserving device lifespan.
Solution Approach 2:
The patent uses partial action by applying dopant doping only to the connection portions rather than the entire active layer. This selective doping provides sufficient electrical enhancement in critical regions while minimizing the harmful effects of dopant exposure on the overall active layer integrity and device longevity.
3Productivity
If amorphous silicon is used as active layer to reduce manufacturing time and cost, then production efficiency is improved, but mobility and current driving ability are limited
Solution Approach 1:
The patent applies local quality by using amorphous oxide semiconductor in connection portions (where high mobility is less critical) and crystalline oxide semiconductor in the channel portion (where high mobility and current driving ability are essential). This spatial differentiation allows manufacturing efficiency benefits from amorphous material while achieving high performance in critical regions through crystalline material.
Solution Approach 2:
The patent uses composite materials by combining amorphous oxide semiconductor and crystalline oxide semiconductor in the active layer. The amorphous portions provide manufacturing efficiency and cost advantages, while the crystalline portions deliver high mobility and excellent current driving ability. This composite structure resolves the contradiction between productivity and device performance.
4Reliability
If polycrystalline silicon is used to achieve high electron mobility and stability, then device performance is improved, but manufacturing cost increases due to additional crystallization processes
Solution Approach 1:
The patent applies local quality by forming crystalline oxide semiconductor only in the channel portion where high electron mobility and stability are critical, while using amorphous oxide semiconductor in connection portions where these properties are less demanding. This selective crystallization reduces the extent of expensive crystallization processing while maintaining high performance where needed.
Solution Approach 2:
The patent uses parameter changes by controlling the crystallization process to achieve partial crystallization rather than complete crystallization of the entire active layer. By adjusting crystallization conditions (temperature, time, atmosphere) to crystallize only the channel portion, the patent reduces manufacturing costs associated with full crystallization while preserving the performance benefits of crystalline structure in critical regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the stability and reliability of thin film transistors by maintaining high mobility and electrical characteristics, reducing manufacturing costs, and extending the device's lifespan through a balanced crystalline and amorphous structure.
Implementation Method 1
a first amorphous portion in which a portion of a crystalline oxide semiconductor layer is amorphized by doping with a dopant
Implementation Method 2
a method for manufacturing this structure involving selective doping and heat treatment
Data Source
AI summary
A thin film transistor can include an active layer; a gate electrode at least partially overlapping with the active layer; and a source electrode and a drain electrode spaced apart from each other and connected to the active layer, respectively. Also, the active layer includes a channel overlapping with the gate electrode; a first connection portion connected to a first side of the channel portion; and a second connection portion connected to a second side of the channel portion. Also, the channel has a crystalline structure, the first connection portion includes a first amorphous portion contacting the channel, and the second connection portion includes a second amorphous portion contacting the channel.