Thin Fo-eWLB Interconnects for High-Density 3D Semiconductor Integration
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Solution Overview
Problem
Conventional through-hole via (THV) substrates in semiconductor devices have limitations such as increased package height, higher manufacturing costs, and insufficient via pitch, which restricts the integration of high-density semiconductor devices and limits the flexibility of 3D semiconductor structures due to their thickness and the laser drilling method used for via formation.
Innovation Solution
The development of a fan-out embedded wafer level ball grid array (Fo-eWLB) with a thin film interconnect structure that features fine pitch interconnects, allowing for the mounting of semiconductor die on both sides of the interconnect structure, which reduces the overall package thickness and increases interconnect density, enabling higher integration and flexibility in 3D semiconductor designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional through-hole via (THV) substrates are used, then via formation is achieved through laser drilling, but the package height increases and manufacturing costs increase
Solution Approach 1:
The patent extracts and eliminates the thick substrate layer characteristic of conventional THV packages. By using a thin film interconnect structure mounted on a carrier substrate rather than forming vias through a thick substrate, the invention removes the unnecessary substrate thickness while retaining the via formation functionality through alternative means (electroless plating and electroplating processes on the thin film structure).
Solution Approach 2:
The patent transitions from a three-dimensional thick substrate structure to a two-dimensional thin film structure. Instead of drilling vertically through a thick substrate to create vias, the invention creates interconnect structures on a thin film plane mounted on a carrier, fundamentally changing the dimensional approach from Z-axis penetration to XY-plane patterning with minimal Z-axis thickness.
2Manufacturing precision
If conventional THV substrates are used, then via formation is achieved, but the via pitch is insufficient for high-density integration
Solution Approach 1:
The patent changes the critical parameter of interconnect pitch from the conventional 100 micrometers or greater in THV substrates to fine pitch interconnects with significantly smaller spacing. This is achieved through the thin film fabrication process using photolithography and electroplating, which enables much finer feature sizes and closer spacing between interconnects, thereby increasing the quantity of interconnects per unit area.
Solution Approach 2:
The patent uses photolithography to create precise patterns of interconnects on the thin film structure. The photomask copying process enables high-precision replication of fine-pitch interconnect patterns, achieving the necessary manufacturing precision for high-density integration that cannot be achieved through laser drilling methods.
3Length of stationary object
If thin film interconnect structure is used, then package thickness is reduced and interconnect density increases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct modular steps: forming the thin film interconnect structure separately, mounting it on the carrier substrate, and then performing subsequent processing. This segmentation allows each step to be optimized independently and simplifies the overall manufacturing complexity by breaking down the complex thin film fabrication into manageable stages that can be performed using standard semiconductor fabrication equipment.
4Manufacturing precision
If laser drilling method is used for via formation, then via creation is achieved, but manufacturing cost increases
Solution Approach 1:
The patent replaces the laser drilling mechanical system with a chemical-electrical system consisting of electroless plating followed by electroplating. Instead of using high-energy laser beams to mechanically ablate material and create vias, the invention uses chemical deposition (electroless plating) to create a conductive base layer, followed by electroplating to build up the interconnect structures, thereby eliminating the need for expensive laser drilling equipment and processes.
Data Source
AI summary
A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die.