Thin-Gate Level Shifter With PFET EOS Protection
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Solution Overview
Problem
Existing voltage level shifter techniques are not suitable for modern integrated circuit devices, as they either require high fabrication costs for thick gate devices or incur increased manufacturing costs and power consumption when using thin gate devices with elevated references, limiting progress towards smaller, faster, and lower power systems.
Innovation Solution
A level shifter using thin gate p-channel field effect transistors configured as pulldown devices to provide electrical over stress (EOS) protection by limiting the voltage across protected devices, eliminating the need for thick gate devices and elevated ground references, thus reducing fabrication and power consumption costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick gate devices are used to provide EOS protection, then device reliability is improved, but fabrication cost increases
Solution Approach 1:
The patent changes the voltage parameter by introducing an elevated reference voltage (e.g., 1.0V above ground) specifically for the thin gate devices. This parameter change allows thin gate devices to operate safely at high I/O voltages without exceeding their EOS thresholds, eliminating the need for expensive thick gate devices while maintaining reliability
Solution Approach 2:
The patent uses thin gate devices (cheaper, shorter-lived compared to thick gate devices) protected by the elevated reference voltage mechanism. This approach substitutes expensive thick gate devices with cheaper thin gate devices that are protected by a simple voltage reference circuit, reducing fabrication costs while providing adequate EOS protection
2Ease of manufacture
If thin gate devices with elevated reference are used, then fabrication cost is reduced, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-establishing the elevated reference voltage before the thin gate devices operate at high voltages. This pre-configured voltage reference is maintained continuously to proactively protect the devices from EOS, preventing damage before it occurs rather than reacting to failures
Solution Approach 2:
The elevated reference voltage acts as an intermediary between the high voltage I/O signals and the thin gate devices. This intermediate voltage level serves as a protective buffer, allowing the thin gate devices to interface with high voltage signals without directly承受 the full voltage stress, thus reducing power consumption compared to using thick gate devices
3Area of moving object
If thin gate devices are used, then device size is reduced, but EOS susceptibility increases
Solution Approach 1:
The patent creates a virtual copy or representation of a protective thick gate device by using the elevated reference voltage mechanism. This virtual protection layer replicates the EOS protection function of thick gate devices without requiring the physical thick gate structure, allowing thin gate devices to achieve the same protection level with smaller size
Data Source
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AI summary
A level shifter circuit, comprising one or more thin gate transistors having source and drain terminals coupled, respectively, to a power supply node and a reference node, where the one or more thin gate transistors have an electrical over stress (EOS) threshold voltage that is lower than a voltage of the power supply applied across two terminals of the one or more thin gate transistors. The circuit further includes a PFET pulldown circuit coupled to an EOS protection circuit to limit the voltage difference across at least two terminals of the one or more thin gate transistors to a voltage below the EOS threshold voltage based on the threshold voltage the PFET.