Thin Glass Substrate for SemOI Signal Linearity
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Solution Overview
Problem
Conventional semiconductor-on-insulator electronic components are limited by parasitic capacitance and current leakage, leading to signal nonlinearity and increased power consumption, which hinders downscaling and efficiency in high-frequency applications like 5G communications and IoT devices.
Innovation Solution
The method involves bonding a semiconductor device wafer with a thin glass or ceramic substrate to a handling wafer, allowing for the exposure of a buried oxide layer and subsequent debonding to form a semiconductor-on-insulator electronic component, which reduces parasitic capacitance and enhances signal linearity, mechanical, and thermal properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor devices are used, then device functionality is achieved, but parasitic capacitance and current leakage increase leading to signal nonlinearity and higher power consumption
Solution Approach 1:
The device is segmented into distinct functional layers: semiconductor device layer, buried oxide layer, and glass substrate. This segmentation isolates the semiconductor devices from the substrate, reducing parasitic capacitance and improving signal linearity while lowering power consumption through reduced current leakage.
Solution Approach 2:
A buried oxide layer is introduced as an intermediary between the semiconductor device layer and the glass substrate. This intermediate layer acts as an electrical insulator that reduces parasitic capacitance and current leakage, thereby improving signal linearity and reducing power consumption.
2Productivity
If device downscaling is pursued to improve performance, then device density increases, but parasitic effects increase leading to signal nonlinearity and loss
Solution Approach 1:
The segmented structure with buried oxide layer physically separates scaled-down devices from the substrate, preventing parasitic effects from increasing proportionally with device density. This allows continued downscaling while maintaining signal linearity.
Solution Approach 2:
The device structure uses composite materials including semiconductor materials for active devices, silicon dioxide for the buried oxide layer, and glass for the substrate. This composite structure provides electrical isolation that maintains signal linearity even as device dimensions are reduced to increase density.
3Reliability
If thin glass or ceramic substrate is used, then parasitic capacitance is reduced and signal linearity is improved, but fabrication complexity increases
Solution Approach 1:
The glass substrate serves multiple functions: it provides mechanical support, acts as a release layer during fabrication, and serves as the final device substrate. The buried oxide layer simultaneously provides electrical isolation and structural support. This multi-functionality reduces overall fabrication complexity despite the thin substrate design.
Solution Approach 2:
The glass substrate is prepared in advance with appropriate thickness and properties before device fabrication. The buried oxide layer is formed as part of the semiconductor fabrication process itself, integrating the isolation function into the device manufacturing flow rather than adding separate processing steps.
4Loss of energy
If material is removed from device wafer to expose buried oxide layer, then SemOI component is formed with reduced parasitic capacitance, but manufacturing steps increase
Solution Approach 1:
Material removal processes such as etching or mechanical removal are used to eliminate excess semiconductor material and expose the buried oxide layer. This extraction of unnecessary material creates the SemOI structure with reduced parasitic capacitance, directly lowering power consumption through reduced current leakage.
Solution Approach 2:
The patent describes mechanical removal methods but the underlying principle allows for substitution with chemical etching processes. This substitution can improve fabrication efficiency by enabling selective removal of material without mechanical contact, reducing steps while achieving the same exposure of the buried oxide layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces power consumption, and improves the electrical and mechanical robustness of the components, enabling better performance in high-frequency applications while maintaining cost-effectiveness.
Implementation Method 1
a device wafer is bonded to a handling wafer... The substrate is adhered to the handling wafer
Implementation Method 2
Material is removed from the device wafer to expose the buried oxide layer
Implementation Method 3
The substrate is debonded from the handling wafer so as to provide an SemOI electronic component
Data Source
AI summary
Embodiments of the disclosure relate to a method for fabricating semiconductor-on-insulator (SemOI) electronic components. In the method, a device wafer is bonded to a handling wafer. The device wafer includes a semiconductor device layer and a buried oxide layer. A substrate is adhered to the handling wafer. The substrate is a glass or a ceramic, and bonding occurs at an interface between the semiconductor device layer and the substrate. Material is removed from the device wafer to expose the buried oxide layer. The substrate is debonded from the handling wafer so as to provide an SemOI electronic component including the substrate, the semiconductor device layer, and the buried oxide layer.