Thin Interposer Semiconductor Package for Stress and Crack Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The use of interposers in semiconductor packages introduces issues such as voids in through substrate vias, abnormal metallization layer routing, bump cold joints, and cracks, which can lead to defective packages due to undetected defects during processing.
Innovation Solution
A semiconductor package structure with a thin interposer substrate (1 μm to 50 μm thick) and a buffer structure, such as a polyimide layer, is used to reduce stress and improve reliability, along with a redistribution structure for electrical routing and conductive vias for improved connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If an interposer is used to allow for reduced chip size and 3D packaging, then chip area and package density are improved, but manufacturing defects such as voids in through substrate vias, abnormal metallization routing, bump cold joints, and cracks increase
Solution Approach 1:
The patent applies preliminary action by performing stress relief processing on the interposer before bonding the chip to it. This advance treatment prevents subsequent manufacturing defects such as voids in through substrate vias, abnormal metallization routing, bump cold joints, and cracks that would otherwise occur during later packaging processes. The stress is relieved in advance, ensuring reliable subsequent processing.
2Strength
If a thick interposer substrate is used to provide structural support, then mechanical strength is improved, but thermal stress increases and electrical performance deteriorates due to increased resistance, inductance, and capacitance
Solution Approach 1:
The patent applies parameter changes by reducing the interposer substrate thickness from conventional dimensions to a specific range of 1-50 micrometers. This parameter change simultaneously achieves multiple objectives: it reduces thermal stress, improves electrical performance by minimizing resistance, inductance, and capacitance, while still maintaining adequate mechanical strength through the optimized thickness range and accompanying stress relief processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The thin interposer substrate reduces thermal stress and improves electrical performance by minimizing resistance, inductance, and capacitance, while the buffer structure enhances package reliability by allowing deformation and preventing cracking.
Implementation Method 1
The thin interposer substrate reduces thermal stress and improves electrical performance by minimizing resistance, inductance, and capacitance
Implementation Method 2
the buffer structure enhances package reliability by allowing deformation and preventing cracking
Data Source
AI summary
One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 μm thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.