Thin-Layer Covering Component with Vertical Interconnects
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Solution Overview
Problem
Existing thin-film package (TFP) components face challenges with connecting faces being on the chip surface, requiring large bumps for soldering and limited space, and non-standard footprint compatibility, which increases component size and complexity.
Innovation Solution
A component with a thin-layer covering and integrated first wiring layer that includes structured conductor traces and solderable connecting pads above the thin-layer covering, allowing for flexible connection distribution and reducing the need for external bumps, enabling compatibility with known TFP packages and improved functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If connecting faces are arranged on the chip surface in conventional TFP packages, then the component structure is simple, but large bumps are required for soldering and valuable space on the carrier surface is consumed
Solution Approach 1:
The patent moves the connecting faces from the horizontal chip surface to the vertical sidewalls of the cavity through structured openings in the thin-layer covering. This dimensional transition from 2D surface arrangement to 3D vertical arrangement eliminates the need for large bumps and preserves valuable carrier surface area while maintaining simple component structure.
2Adaptability or versatility
If connecting faces are arranged on the chip surface, then the component can be packaged in conventional TFP packages, but the footprint compatibility with standardized components is limited and additional space is required for conductor paths
Solution Approach 1:
By relocating connecting faces to the vertical sidewalls through structured openings, the patent enables flexible arrangement of connection points without being constrained by the horizontal chip surface layout. This allows adaptation to standardized component footprints while minimizing carrier surface area consumption.
3Reliability
If bumps are used to solder the component to a circuit board, then electrical connection is achieved, but the bump stand-off height must be at least the height of the thin-layer covering plus tolerance, increasing overall component height
Solution Approach 1:
The patent transitions the connection interface from the horizontal top surface to the vertical sidewalls through structured openings. This allows solder connections to be made at the cavity opening level rather than requiring bumps to bridge the entire thin-layer covering height, thereby reducing the required stand-off height and overall component height while maintaining solder connection reliability.
4Adaptability or versatility
If the distribution of connecting faces is adapted to a required footprint, then standardized component compatibility is improved, but conductor paths require additional space on the carrier surface
Solution Approach 1:
By moving connecting faces to the vertical sidewalls, the patent decouples the connection point locations from the horizontal chip surface area. This allows conductor paths to be routed more efficiently and reduces the additional space required on the carrier surface while maintaining adaptability to required footprints for standardized components.
Data Source
Figure 1A~3
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Figure 6a~6e
AI summary
A component (B) is specified which comprises a functional structure (FS) on a carrier (TR) that is spanned by a thin-layer covering (DSA) resting on said carrier. A first wiring layer (VE1) is applied onto or in the thin-layer covering and comprises structured conductor traces that are connected with the functional structure.