Thin-Layer Covered MEMS Component With Bottom-Routed Wiring
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Solution Overview
Problem
Existing thin-film package technologies for MEMS components face challenges with space inefficiency due to the need for bumps for soldering, which require significant area and do not align with standard footprints, leading to increased component size and cost, especially in miniaturized designs.
Innovation Solution
A component with a thin-layer covering and a planarization layer, where a wiring level is applied over the thin-layer covering, allowing for direct electrical connections and reducing the need for surface area on the carrier, enabling flexible placement of connecting pads and minimizing component size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bumps are used for soldering connections on the chip surface, then electrical connections to the circuit environment are achieved, but the component requires significant surface area and increased construction height
Solution Approach 1:
The patent moves the electrical connection interface from the horizontal chip surface (2D plane) to the vertical dimension by routing connections through the thickness of the component. Through-silicon vias and conductive layers embedded within the substrate allow electrical connections to be made from the bottom surface, eliminating the need for surface-mounted bumps and reducing the required carrier footprint.
Solution Approach 2:
Instead of making connections from the top surface of the chip where the functional elements are located, the patent inverts the connection approach by providing access to electrical contacts from the bottom surface of the substrate. This inversion allows connections to be made underneath the component rather than requiring surface area above it.
2Ease of manufacture
If the connecting areas are arranged on the chip surface, then electrical connections are possible, but the component footprint increases and does not align with standardized footprints
Solution Approach 1:
The patent transitions the connection interface from the horizontal plane to the vertical dimension by embedding conductive pathways within the substrate thickness. This allows the top surface to maintain a clean, standardized footprint while electrical connections are established through the substrate to the bottom surface, enabling compatibility with standardized mounting patterns.
Solution Approach 2:
The substrate serves multiple functions: it provides mechanical support for the functional elements, routes electrical signals through its thickness, and presents a standardized connection interface at the bottom surface. This multi-functionality allows the same substrate structure to accommodate various functional configurations while maintaining a universal footprint.
3Reliability
If bumps with sufficient stand-off are used for soldering, then reliable electrical connections are achieved, but the construction height of the component increases
Solution Approach 1:
Instead of extending connections upward from the chip surface with tall bumps to achieve sufficient stand-off, the patent inverts the approach by providing electrical access from the bottom surface. This eliminates the need for vertical bump structures and reduces the overall construction height while maintaining reliable solder connections.
4Adaptability or versatility
If conductor paths are added on the carrier surface to adapt to required footprint, then standardized footprints are achieved, but additional space is consumed and component size increases
Solution Approach 1:
The patent eliminates the need for surface conductor paths by routing all electrical connections through the vertical dimension of the substrate. Functional elements are electrically connected to bottom-surface contacts via conductive layers and vias within the substrate thickness, requiring no additional horizontal space for trace routing.
Data Source
Figure 1A~1E
Figure 2A~2E
Figure 2F~2J
AI summary
A component (B) comprising a carrier (TR), on which a functional structure (FS) is covered by a thin-layer covering (DSA) spanning across and resting on the carrier. On a planarization layer arranged above the thin-layer covering (DSA), a wiring level (M1, M2) is realized, which comprises structured conductor paths and which is connected via through-connections to the functional structure (FS).