Thin-Layer Covered Component With Side Contact Routing
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Solution Overview
Problem
MEMS and micro-acoustic components with thin-film packages face challenges in connecting faces arrangement, requiring large bumps for soldering and limited space on miniaturized components, which increases component size and costs due to non-standard footprint and conductor path constraints.
Innovation Solution
A component with a thin-layer covering and a planarization layer, featuring a wiring level with structured conductor paths that connects functional structures directly, allowing for arbitrary contact placement and reducing the need for external connectors, thus minimizing component size and saving surface space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If connecting faces are arranged on the chip surface between thin-layer coverings, then soldering connection is enabled, but bump height must be at least the height of the thin-layer covering plus tolerance, increasing component height and space requirements
Solution Approach 1:
The patent moves the connecting faces from the horizontal chip surface to the vertical side surface of the carrier, utilizing a different spatial dimension. This allows bumps to connect directly to the side surface without needing to clear the height of thin-layer coverings, thereby reducing the required bump height and overall component height while maintaining soldering functionality.
Solution Approach 2:
The patent introduces a relief structure on the side surface of the carrier as an intermediary element. This relief structure provides a dedicated connection surface that mediates between the bumps and the carrier, enabling direct electrical connection without requiring bumps to extend through or above the thin-layer coverings.
2Ease of operation
If connecting faces are arranged on the carrier surface, then electrical connection is enabled, but conductor paths and connecting faces take up additional space on the carrier surface, increasing component footprint
Solution Approach 1:
The patent relocates connecting faces from the two-dimensional chip surface to the three-dimensional side surface of the carrier. This dimensional transition removes the connection structures from the limited carrier surface area, freeing up valuable real estate for active components while maintaining all necessary electrical connection functionality through the side surface.
Solution Approach 2:
The patent extracts the connecting faces and conductor paths from the carrier surface plane and relocates them to the side surface. This separation removes the space-consuming conductor paths from the carrier surface, allowing the active surface to be dedicated entirely to functional structures without being encroached upon by connection infrastructure.
3Ease of operation
If connecting faces are arranged on the chip surface, then connection to circuit environment is enabled, but arbitrary placement of contacts is constrained by existing footprint requirements
Solution Approach 1:
By moving connecting faces to the side surface of the carrier, the patent creates a new spatial plane for contact arrangement that is independent of traditional footprint constraints. This enables completely flexible placement of contacts according to circuit requirements without being limited by standardized footprint patterns, as the side surface offers unrestricted positioning freedom.
Solution Approach 2:
The patent enables dynamic and flexible arrangement of connecting faces on the side surface, allowing the connection layout to be optimized for each specific application rather than being fixed by standardized footprints. This dynamic positioning capability provides adaptability for different circuit environments and connection requirements.
Data Source
AI summary
A component (B) comprising a carrier (TR), on which a functional structure (FS) is covered by a thin-layer covering (DSA) spanning across and resting on the carrier. On a planarization layer arranged above the thin-layer covering (DSA), a wiring level (M1, M2) is realized, which comprises structured conductor paths and which is connected via through-connections to the functional structure (FS).