Thin Metal Interconnect Fabrication via Residue-Free Via Etching
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Solution Overview
Problem
Advanced MRAM and STT-MRAM devices face manufacturing yield and device failure issues due to residues and redepositions from plasma etching and photoresist/BARC stripping processes, which are difficult to remove using conventional cleaning methods, leading to poor quality word line via interconnections and increased metal resistance.
Innovation Solution
A process flow involving a thin single layer of silicon nitride or silicon carbide as the interlevel dielectric, with a specific reactive ion etch and post-etch cleaning sequence, including a dual frequency capacitive etch reactor and a three-step wet cleaning process, to form residue-free via openings and ensure effective removal of etch residues, thereby maintaining high performance and device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional plasma etching and photoresist/BARC stripping processes are used, then via openings can be formed, but residues and redepositions are generated that are difficult to remove
Solution Approach 1:
The etching process is divided into multiple sequential steps with different gas chemistries: first CHF3 for initial etching, then CF4 for main etching, and finally a combined CHF3/CF4 step. Each step targets specific removal requirements, segmenting the overall process to minimize residue generation at each stage while maintaining effective via opening formation.
Solution Approach 2:
The patent systematically varies process parameters including gas flow rates (CHF3: 10-50 sccm, CF4: 50-200 sccm), pressure (20-100 mTorr), and power (50-200 W) across different etching steps. These parameter changes optimize the balance between etching efficiency and residue minimization for each specific process stage.
2Reliability
If thin interlayer dielectric is used to enhance magnetic field strength, then device performance improves, but residue removal becomes more difficult
Solution Approach 1:
A fluorocarbon-based protective coating is deposited on the wafer surface before the etching process. This preliminary action creates a protective layer that prevents excessive residue formation during subsequent etching steps, particularly important when working with thin ILD where residue removal is more challenging.
Solution Approach 2:
The patent introduces a fluorocarbon-based protective coating as an intermediary layer during the etching process. This coating acts as a mediator that protects the thin ILD and copper surfaces from direct plasma damage and residue formation, enabling effective processing of thin dielectric layers.
3Reliability
If copper is used for word line to reduce resistance, then electrical performance improves, but copper oxide formation increases during plasma processing
Solution Approach 1:
The etching process uses fluorocarbon-based gases (CHF3, CF4) that create an inert fluorocarbon plasma environment. This inert atmosphere prevents copper oxidation during the etching process by replacing oxygen with fluorocarbon species, thereby protecting the copper word line while maintaining etching effectiveness.
Solution Approach 2:
The patent converts the potential harm of plasma exposure to copper by using fluorocarbon-based chemistry that actually protects copper from oxidation. The fluorocarbon plasma, which could potentially damage copper, is instead used to create a protective environment that prevents oxide formation while enabling effective dielectric etching.
4Manufacturing precision
If multiple etching steps are used to reduce residues, then via quality improves, but process complexity increases
Solution Approach 1:
The patent combines multiple functions into integrated process steps. For example, the final etching step uses a combined CHF3/CF4 chemistry that simultaneously performs dielectric etching and copper protection. The protective coating deposition and etching processes are also integrated into a single chamber sequence, reducing overall process complexity while maintaining via quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces residue buildup and improves the quality of word line via interconnections, enhancing manufacturing yield and device performance by ensuring a strong magnetic field on the MTJ element and preventing copper oxide formation.
Implementation Method 1
a process flow involving a thin single layer of silicon nitride or silicon carbide as the interlevel dielectric, with a specific reactive ion etch
Implementation Method 2
specific reactive ion etch and post-etch cleaning sequence
Implementation Method 3
post-etch cleaning process to remove etch residues and re-deposited material
Implementation Method 4
copper wires in MRAM devices... word line to conduct electric current and generate a WL magnetic field
Implementation Method 5
The electrical resistance for tunneling current across the tunnel barrier layer depends on the relative magnetic directions of the pinned and free layers... referred to as a magnetoresistance effect that can be used to store binary information
Data Source
AI summary
A scheme for forming a thin metal interconnect is disclosed that minimizes etch residues and provides a wet clean treatment for via openings. A single layer interlayer dielectric (ILD), BARC, and photoresist layer are successively formed on a substrate having a copper layer that is coplanar with a dielectric layer. In one embodiment, the ILD is silicon nitride with 100 to 600 Angstrom thickness. After a via opening is formed in a photoresist layer above the copper layer, a first RIE process including BARC main etch and BARC over etch steps is performed. Then a second RIE step transfers the opening through the ILD to uncover the copper layer. Photoresist and BARC are stripped with oxygen plasma and a low DC bias. Wet cleaning may involve a first ST250 treatment, ultrasonic water treatment, and then a third ST250 treatment. A bottom electrode layer may be deposited in the via opening.