Thin MLCC Dielectric Grain Segmentation for Permittivity and DC-Bias
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Solution Overview
Problem
High-capacitance multilayer ceramic capacitors face challenges in maintaining high permittivity while ensuring excellent DC-bias characteristics, as reducing grain size to prevent short-circuit defects can lead to deteriorated DC-bias characteristics, and increasing permittivity through larger grains may compromise capacitance.
Innovation Solution
A multilayer ceramic capacitor design with dielectric grains sized between 50 nm and 450 nm, distributed in sections within a 0.025 to 0.20 fraction, and a dielectric layer thickness of 0.8 μm or less, using a dielectric ceramic composition that includes a barium titanate base material and accessory ingredients to achieve high permittivity and improved DC-bias characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of the grain is decreased by applying fine BaTiO3 powder to prevent short-circuit defects, then reliability is improved, but permittivity decreases making it difficult to implement capacitance
Solution Approach 1:
The patent applies different grain size ranges in different sections of the dielectric layer. The first section (bottom) has grains of 50-150 nm for short-circuit prevention, while the second section (top) has grains of 150-450 nm for high permittivity. This local differentiation resolves the contradiction by allowing each region to optimize for its specific function.
Solution Approach 2:
The dielectric layer is segmented into multiple sections with different grain size distributions. This segmentation allows the patent to simultaneously achieve short-circuit defect prevention in the bottom section and high permittivity in the top section, resolving the contradiction between reliability and capacitance implementation.
2Quantity of substance
If the size of the grain is increased to increase permittivity, then capacitance is improved, but DC-bias characteristics deteriorate
Solution Approach 1:
The patent assigns different grain size characteristics to different locations: larger grains (150-450 nm) in the top section for high permittivity, and smaller grains (50-150 nm) in the bottom section for good DC-bias characteristics. This local quality differentiation allows simultaneous optimization of both parameters.
Solution Approach 2:
By segmenting the dielectric layer into sections with different grain size distributions, the patent achieves high overall permittivity through the top section while maintaining excellent DC-bias characteristics through the bottom section with smaller grains.
3Productivity
If the thickness of the dielectric layer is reduced to increase capacitance, then productivity is improved, but short-circuit defects increase
Solution Approach 1:
The bottom section of the thin dielectric layer has smaller grains (50-150 nm) specifically engineered to prevent short-circuit defects, while the overall layer remains thin (0.8 μm or less) for high capacitance density. This local quality control enables thin-layer high-capacitance devices without sacrificing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high nominal and effective permittivity, high-temperature withstand voltage, and a temperature coefficient of capacitance within ±15% at 85°C, while maintaining high capacitance and reliability under DC-bias conditions.
Implementation Method 1
a fraction of the dielectric grains in each of the sections within a range of 50 nm to 450 nm is within a range of 0.025 to 0.20... high nominal and effective permittivity
Data Source
AI summary
A multilayer ceramic capacitor includes: a ceramic body in which dielectric layers and first and second internal electrodes are alternately stacked; and first and second external electrodes formed on an outer surface of the ceramic body and electrically connected to the first and second internal electrodes, respectively. In a microstructure of the dielectric layer, dielectric grains are divided by a dielectric grain size into sections each having an interval of 50 nm, respectively, a fraction of the dielectric grains in each of the sections within a range of 50 nm to 450 nm is within a range of 0.025 to 0.20, and a thickness of the dielectric layer is 0.8 μm or less.