Thin-Oxide On-Chip LDO With Level Shifting for Gate Oxide Stress
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Solution Overview
Problem
Existing CMOS technologies face challenges with thin-oxide gate oxides due to overstressing from high gate-to-source voltages, leading to stress-induced leakage currents and reduced transistor lifetime, particularly in advanced fabrication processes like 2 nm and below.
Innovation Solution
Development of high-voltage, low-power, temperature-dependent thin-oxide on-chip LDO regulators with level shifters and power gating features to maintain desired gate-to-source voltages within safe limits, using thin-oxide MOSFETs to regulate voltage swings and prevent overvoltage violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate oxide thickness is reduced to scale with channel length, then short channel effects are controlled, but gate leakage current increases due to quantum-mechanical tunneling
Solution Approach 1:
The patent divides the gate oxide structure into multiple segments: a thin gate oxide layer (3nm or less) for high-speed operation and a thick interlayer dielectric layer (greater than 3nm) for stress protection. This segmentation allows the thin oxide to enable fast switching while the thick dielectric prevents tunneling-induced leakage and stress damage, resolving the contradiction between speed and leakage.
Solution Approach 2:
The patent applies a thick interlayer dielectric layer (greater than 3nm) over the thin gate oxide layer before the device operates. This thick dielectric acts as a cushion that prevents stress-induced leakage and protects the thin oxide from degradation, allowing the thin oxide to function at high speeds without suffering from the harmful effects of quantum tunneling and stress.
2Adaptability or versatility
If thick-oxide circuitry voltages are applied to thin-oxide circuitry, then interface compatibility is achieved, but gate oxide overstress and reliability reduction occur
Solution Approach 1:
The patent applies a thick interlayer dielectric layer (greater than 3nm) over the thin gate oxide layer before the device operates. This thick dielectric acts as a cushion that prevents stress-induced leakage and protects the thin oxide from degradation, allowing the thin oxide to function at high speeds without suffering from the harmful effects of quantum tunneling and stress.
Solution Approach 2:
The thick interlayer dielectric layer serves as an intermediary between the thin gate oxide layer and the high-voltage thick-oxide circuitry. It mediates the stress and voltage effects, allowing the thin-oxide circuit to interface with high-voltage systems without direct exposure to damaging stress, thus maintaining both compatibility and reliability.
3Productivity
If thin-oxide MOSFETs are used in 2 nm processes, then fabrication scalability is improved, but vulnerability to stress-induced leakage and reduced lifetime increase
Solution Approach 1:
The patent divides the dielectric structure into a thin gate oxide layer (3nm or less) for high-speed operation and a thick interlayer dielectric layer (greater than 3nm) for stress protection. This segmentation allows the thin oxide to enable fast switching while the thick dielectric prevents tunneling-induced leakage and stress damage, resolving the contradiction between speed and leakage.
Solution Approach 2:
The patent applies a thick interlayer dielectric layer (greater than 3nm) over the thin gate oxide layer before the device operates. This thick dielectric acts as a cushion that prevents stress-induced leakage and protects the thin oxide from degradation, allowing the thin oxide to function at high speeds without suffering from the harmful effects of quantum tunneling and stress.
Data Source
AI summary
Techniques to utilize thin-oxide devices, such as gate-all-around metal-oxide-semiconductor field-effect transistors (MOSFETs), in high voltage environments, such as to provide a high-voltage based low-power, temperature dependent, thin-oxide-only on-chip high current low drop out (LDO) regulator in a system-on-chip (SoC), such as provide power to configuration random-access memory (CRAM) cells distributed throughout configurable/programmable circuitry. Thin-oxide only circuitry may include thin-oxide-only amplifier circuitry, thin-oxide-only power gate circuitry, thin-oxide-only level shifters that shift voltage swings of control signals to voltage domains of the power gate circuitry, and thin-oxide-only clamp circuitry.