Extremely Thin Package Grinding EMC Protection
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Solution Overview
Problem
Existing chip manufacturing assembly processes result in thick packages due to the use of Epoxy Molding Compound (EMC) fillers, which contribute to increased dimensions and are not effectively reduced, leading to issues with light emission leakage and moisture penetration.
Innovation Solution
A grinding process is introduced to reduce the package thickness by exposing the backside of the integrated circuit or applying adhesion tape, allowing for thinner package structures such as extremely thin DFN and QFN packages, while protecting the chip from light emission and moisture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If EMC fillers are applied to cover the entire area of the device, then the integrated circuit is protected from light emission induced leakage and moisture penetration, but the overall package thickness increases
Solution Approach 1:
The EMC application is segmented into two distinct stages: first applying EMC to the front side for light and moisture protection, then applying additional EMC to the back side after grinding to achieve the desired thin profile. This segmentation allows the package to be thin overall while still providing comprehensive protection on both surfaces.
Solution Approach 2:
The backside EMC application is performed as a preliminary action after grinding but before final assembly completion. This ensures that the protection layer is in place before the device is finalized, allowing for thin packaging while maintaining reliability requirements.
2Length of stationary object
If the package thickness is reduced to achieve extremely thin structures, then device dimensions are improved, but protection from light emission and moisture penetration becomes insufficient
Solution Approach 1:
The protection strategy is segmented into front-side EMC application for initial protection and back-side EMC application after grinding for final protection. This ensures that even in an extremely thin package, both surfaces receive adequate protective coating.
Solution Approach 2:
The EMC application parameters are changed from a single thick layer to multiple thin layers applied at different stages. The front side receives EMC first, then the package is ground thin, and finally the back side receives EMC to complete the protection, achieving both thinness and reliability.
3Reliability
If adhesion tape is applied on the backside to protect the chip, then light emission induced leakage and moisture penetration are prevented, but the manufacturing process complexity increases
Solution Approach 1:
The protective layer parameter is changed from adhesion tape to EMC material applied as a coating. This maintains the protective function while integrating into the existing EMC application process, avoiding the need for separate tape application and removal steps.
Solution Approach 2:
The EMC material serves multiple functions: it provides structural support, electrical insulation, and protection from light emission and moisture penetration. By using EMC for all these purposes, the need for separate adhesion tape is eliminated, reducing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The grinding process achieves significantly thinner package structures, reducing overall device thickness and addressing leakage and moisture issues, with optional adhesion tape providing additional protection for sensitive devices.
Implementation Method 1
A grinding process is introduced to reduce the package thickness by exposing the backside of the integrated circuit
Data Source
AI summary
Techniques for achieving extremely thin package structures are disclosed. In some embodiments, a device comprises an integrated circuit connected to a leadframe or substrate via connections and EMC (Epoxy Molding Compound) surrounding the integrated circuit except at a backside of the integrated circuit and connecting areas via which the integrated circuit is connected to the leadframe or substrate.