Thin Semiconductor Package With Vertical Terminal Stacking
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Solution Overview
Problem
Semiconductor packages face a challenge in increasing the number of external connection terminals while maintaining a reduced size and manufacturing cost, as larger planar areas are required to accommodate more terminals, and existing fan-out packages struggle to achieve high pattern density and thin thickness simultaneously.
Innovation Solution
The semiconductor package design incorporates a lower connection structure, an intermediate connection structure, and an upper connection structure with a sealing layer, insulating layers, conductive pattern layers, and vias to connect the semiconductor chip to external terminals, ensuring a high pattern density and reduced thickness while maintaining a low manufacturing cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of external connection terminals is increased, then the performance of the semiconductor package is improved, but the planar area occupied by the package increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of connection terminals to a three-dimensional vertical stacking architecture. Multiple connection structures are arranged in different layers (first connection structure, second connection structure, third connection structure) along the vertical direction, allowing numerous external connection terminals to be accommodated within a compact planar footprint by utilizing the vertical dimension for terminal distribution and interconnection.
Solution Approach 2:
The patent implements a nested hierarchical structure where connection structures are organized in multiple levels. The first connection structure is positioned at a lower level, the second connection structure at an intermediate level, and the third connection structure at an upper level. Each connection structure contains multiple connection terminals that are electrically interconnected through vertical vias and conductive pathways, creating a nested arrangement that maximizes terminal density within the package volume.
2Area of stationary object
If the planar area of the semiconductor package is reduced, then the manufacturing cost is reduced, but the number of external connection terminals that can be accommodated decreases
Solution Approach 1:
The patent resolves this contradiction by moving the terminal arrangement from a single-plane configuration to a multi-layer vertical configuration. The connection structures are distributed across multiple vertical levels, enabling a high density of external connection terminals to be packed into a small planar area. This dimensional transition allows the package to maintain a compact footprint while achieving high terminal count through vertical stacking of connection layers.
Solution Approach 2:
The patent segments the connection terminal arrangement into multiple discrete connection structures (first, second, and third connection structures) positioned at different vertical levels. Each connection structure contains a subset of the total external connection terminals, and these segmented structures are electrically interconnected through vertical conductive pathways. This segmentation enables efficient space utilization and facilitates the accommodation of numerous terminals within a reduced planar area.
3Length of stationary object
If the thickness of the semiconductor package is reduced, then the overall size is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent achieves reduced thickness by optimizing the vertical arrangement of multiple connection structures and minimizing the spacing between layers. The first, second, and third connection structures are positioned in close vertical proximity, with thin insulating layers and conductive vias connecting them. This compact vertical stacking in the thickness direction reduces the overall package height while maintaining the multi-layer connection architecture, thereby reducing size without proportionally increasing manufacturing complexity.
4Quantity of substance
If high pattern density is achieved in the upper connection structure, then the number of external connection terminals is increased, but the thickness increases
Solution Approach 1:
The patent applies local quality by varying the density and configuration of connection structures at different vertical levels. The upper connection structure (third connection structure) is designed with high pattern density to maximize the number of external connection terminals in a compact area. Meanwhile, the intermediate (second connection structure) and lower (first connection structure) connection structures have different density configurations, allowing the upper layer to achieve high terminal density without proportionally increasing the overall thickness, as each layer contributes differently to the total terminal count.
Data Source
AI summary
A semiconductor package includes; a lower connection structure, a semiconductor chip on the lower connection structure, an intermediate connection structure on the lower connection structure, a sealing layer covering the semiconductor chip, and an upper connection structure including a first upper insulating layer on the sealing layer, a first upper conductive pattern layer on the first upper insulating layer, and a first upper via penetrating the first upper insulating layer to directly connect the first upper conductive pattern layer to the intermediate connection structure. A height from an upper surface of the lower connection structure to an upper surface of the sealing layer is less than or equal to a maximum height from the upper surface of the lower connection structure to an upper surface of the intermediate connection structure.