Thin Semiconductor Device Without Substrate

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor devices face limitations in reducing thickness due to the use of substrates supporting wiring patterns, and the flip-chip connection method has reached its thickness reduction limits.

Innovation Solution

A semiconductor device and manufacturing method that omit the substrate by using a first insulating layer with openings, a first wiring pattern, a second insulating layer with via holes, and a semiconductor element with electrodes in the via holes, connected via conductive material, and sealed with underfill and sealing resins, allowing for direct mounting on the second insulating layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If a substrate supporting wiring pattern is used, then electrical connectivity is maintained, but device thickness cannot be further reduced

Engineering Contradiction:
Improvedevice thicknessVSAvoidsubstrate structure
Core Design Contradiction:
Length of moving objectVSDevice complexity

Solution Approach 1:

The patent extracts and removes the substrate from the semiconductor device structure, retaining only the essential insulating layers and wiring patterns needed for electrical connectivity. This eliminates the thickness contribution of the substrate while maintaining the core functional elements.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from a three-dimensional substrate-based structure to a planar, layered structure where wiring patterns are formed directly on insulating layers. This dimensional simplification enables extreme thinness by eliminating the vertical thickness of the substrate.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Length of moving object

If substrate is omitted for thickness reduction, then device thickness is reduced, but manufacturing handling becomes difficult

Engineering Contradiction:
Improvedevice thicknessVSAvoidmanufacturing handling
Core Design Contradiction:
Length of moving objectVSEase of manufacture

Solution Approach 1:

The patent applies preliminary actions by forming carrier tapes with adhesive layers before mounting the insulating layers and wiring patterns. These carrier tapes provide temporary support during manufacturing processes, making handling easy, and are removed after the structure is stabilized with sealing resin.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces carrier tapes as intermediary elements that facilitate manufacturing handling. These tapes serve as temporary carriers that enable easy manipulation and positioning of the thin insulating layer structures during assembly, then are discarded after serving their purpose.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Length of moving object

If flip-chip connection method is used, then device thickness is reduced, but further thickness reduction reaches limit

Engineering Contradiction:
Improvedevice thicknessVSAvoidconnection reliability
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent inverts the traditional approach by mounting the semiconductor element with electrodes facing upward on the insulating layer, rather than using conventional flip-chip bonding where elements are bonded face-down. This inverted configuration eliminates the need for thick underfill resin and bonding interfaces, enabling extreme thinness while maintaining connection reliability through direct electrode contact with wiring patterns.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS7936061B2Semiconductor device and method of manufacturing the same
Publication Date: 2011.05.03 SHINKO ELECTRIC IND CO LTD
  • US7936061B2 patent drawing
  • US7936061B2 patent drawing
  • US7936061B2 patent drawing

AI summary

A semiconductor device includes: a first insulating layer having an opening therethrough; a first wiring pattern disposed on the first insulating layer; an external connection terminal provided on a portion of the first wiring pattern exposed from the opening; a second insulating layer which covers the first wiring pattern and having via holes therethrough; a second wiring pattern disposed within the second insulating layer and electrically connected to the first wiring pattern via a conductive material filled in at least one of the via holes; a semiconductor element having an electrode thereon and mounted on the second insulating layer to be electrically connected to the first wiring pattern through the electrode disposed in at least one of the via holes; an underfill resin filled between the semiconductor element and the second insulating layer; and a sealing resin portion which seals the semiconductor element.