Thin SOI Auxiliary Gated Transistor for Leakage Reduction
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Solution Overview
Problem
Conventional high voltage high power transistors fabricated on bulk silicon or compound semiconductors are not suitable for high temperature applications due to large device area requirements and high leakage currents, which are exacerbated by thick silicon films needed in existing SOI designs, making them costly and inefficient.
Innovation Solution
A high voltage high-power device structure is fabricated using a thin active silicon layer on SOI wafers with a cascode configuration, including a control gate and auxiliary gate, which minimizes leakage current and allows for high frequency operation by adjusting the surface electrical field, and is fabricated using a method that selectively forms raised source, drain, and lightly doped drain regions with precise doping densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DMOST devices are fabricated on bulk silicon with thick silicon films, then high voltage capability is achieved, but leakage current increases exponentially with temperature and device area becomes very large
Solution Approach 1:
The patent changes the silicon film thickness parameter from conventional thick films (1.5-12 μm) to a thin film (20 nm) in the active region. This parameter change reduces the volume of the junction depletion region, thereby minimizing leakage current generation while maintaining high voltage capability through the SOI structure and auxiliary gate configuration.
Solution Approach 2:
The patent segments the transistor structure by introducing an auxiliary gate that divides the channel into two regions: a thin active silicon region (20 nm) for low leakage and a thicker drift region for high voltage sustainment. This segmentation allows each region to optimize its function independently.
2Reliability
If conventional DMOST devices use thick top active silicon films (1.5-12 μm), then high voltage capability is maintained, but leakage current increases and device area becomes very large
Solution Approach 1:
The patent dramatically reduces the top active silicon film thickness from conventional 1.5-12 μm to just 20 nm in the active region. This parameter change enables compact device area while maintaining high voltage capability through the SOI structure and auxiliary gate, directly resolving the contradiction between voltage capability and area.
3Ease of manufacture
If conventional DMOST devices are fabricated on SOI with thick silicon films (1.5-12 μm), then fabrication compatibility is achieved, but leakage current increases exponentially with temperature
Solution Approach 1:
The patent changes the silicon film thickness parameter to 20 nm in the active region, which minimizes the volume of the junction depletion region. This reduces thermal generation of carriers and leakage current at high temperatures while remaining compatible with standard SOI fabrication processes.
Solution Approach 2:
The patent applies different silicon film thicknesses to different regions: a thin 20 nm active region for low leakage and a thicker drift region for high voltage sustainment. This local quality differentiation allows the device to achieve low leakage at high temperatures while maintaining fabrication compatibility.
4Productivity
If conventional DMOST devices use very short channel length for high current, then current capability is improved, but breakdown voltage becomes very low
Solution Approach 1:
The patent segments the channel into two functional regions separated by an auxiliary gate: a short channel region (0.5-2 μm) for high current capability and a long drift region for high breakdown voltage. This segmentation allows the device to achieve both high current and high voltage capability simultaneously, resolving the contradiction.
Solution Approach 2:
The auxiliary gate acts as an intermediary element that enables the coexistence of short channel and long drift region in the same device. It electrically isolates the two regions while allowing them to work together, achieving both high current and high breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the fabrication of high power devices with reduced leakage current and area requirements, allowing for efficient high temperature operation and integration of power and digital circuits without large isolation areas, while being cost-effective by utilizing thin active silicon films.
Implementation Method 1
a very thin top active silicon film... The volume of the junction depletion layer would be small enough to not generate large leakage current even at high temperatures
Implementation Method 2
The surface electrical field at the control gate-to-drain edge and at the auxiliary gate drain edge can be adjusted not only by the dopant density and length of the LDD region, but also by the auxiliary gate voltage
Data Source
AI summary
A silicon (Si)-on-insulator (SOI) high voltage transistor is provided with an associated fabrication process. The method provides a SOI substrate with a Si top layer. A control channel and an adjacent auxiliary channel are formed in the Si top layer. A control gate overlies the control channel and an auxiliary gate overlies the auxiliary channel. A source region is formed adjacent the control channel, and a lightly doped drain (LDD) region is interposed between the auxiliary channel and the drain. An interior drain region is interposed between the control and auxiliary channels. Typically, the Si top layer has a thickness in the range of 20 to 1000 nm. In one aspect, the Si top layer in the source, control channel, interior drain, and auxiliary channel regions is thinned to a thickness in the range of 5 to 200 nm, and raised source, drain, LDD, and interior drain regions are formed.