Thin Stack Packages via Vertical Bump Interconnects
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Solution Overview
Problem
The challenge in the semiconductor industry is to create compact, high-capacity semiconductor packages for mobile systems, where scaling down semiconductor packages while maintaining electrical connectivity and preventing warping and contact failures due to reduced thickness.
Innovation Solution
A thin stack package design featuring a substrate with first and second circuit patterns at different levels, where first and second semiconductor chips are vertically stacked with bumps extending through the substrate to connect electrically, and an adhesive layer is used to prevent warping and ensure reliable contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor packages are scaled down in size to meet mobile system requirements, then the package size is reduced, but warping and contact failures occur due to reduced thickness
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration, where semiconductor chips are vertically stacked and connected via bumps that extend through the substrate thickness. This dimensional change enables compact packaging while maintaining reliable electrical connections by utilizing the vertical dimension rather than relying solely on planar trace routing.
Solution Approach 2:
The patent implements a nested structure where semiconductor chips are stacked one on top of another, with connection bumps extending through intermediate substrates. Each chip-bump-substrate combination is nested within the overall package structure, allowing multiple functional layers to be integrated in a compact vertical arrangement that maintains connection reliability despite reduced overall package dimensions.
2Quantity of substance
If multiple semiconductor chips are placed in a single package to increase capacity, then the package capacity is increased, but the package complexity increases
Solution Approach 1:
The patent merges multiple semiconductor chips into a single integrated stack package, where chips are vertically stacked and electrically connected through bumps that penetrate the substrate. This combining approach achieves high capacity in a compact form factor while reducing overall package complexity compared to alternative multi-chip configurations by utilizing standardized bump connections and layered substrate structures.
3Length of stationary object
If the substrate thickness is reduced to create thinner packages, then the package thickness is reduced, but warping occurs affecting manufacturing precision
Solution Approach 1:
The patent employs composite substrate structures with multiple layers including dielectric layers, conductive bumps, and adhesive layers. This composite construction provides structural reinforcement that prevents warping in thin substrates, enabling reduced substrate thickness while maintaining manufacturing precision through the combined mechanical properties of different materials working together.
Data Source
AI summary
The stack package includes a substrate body layer having a top surface and a bottom surface, first circuit patterns disposed on the bottom surface of the substrate body layer, second circuit patterns disposed on the top surface of the substrate body layer, a first semiconductor chip including first bumps, and a second semiconductor chip including second bumps. The first bumps extend through the substrate body layer to be electrically coupled to the first circuit patterns, and the second bumps extend past sidewalls of the first semiconductor chip to be electrically coupled to the second circuit patterns. The second semiconductor chip is stacked on the first semiconductor chip.