Thin Substrate CSP via Preliminary Action
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Solution Overview
Problem
Conventional chip scale packaging (CSP) methods face challenges such as handling difficulties with thin leadframes, inadequate insulation leading to terminal breakage, warpage due to differing thermal expansion coefficients, and misalignment of terminals during the semiconductor chip mounting process, resulting in reliability issues and increased cycle time.
Innovation Solution
The method involves using a single unit leadframe with terminals protruding from its surface, where the semiconductor chip is attached and encapsulated before the leadframe is separated into independent terminals, minimizing handling issues and reducing warpage-related delamination by maintaining terminal connection during molding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the leadframe is made very thin to reduce package thickness, then the package thickness is reduced, but the leadframe becomes difficult to handle during the etching process and the independent terminals are left unsupported
Solution Approach 1:
The patent applies preliminary action by performing the chip mounting and molding steps before etching the leadframe into independent terminals. This sequence ensures that the thin leadframe is supported by the chip and molding compound during the etching process, preventing handling difficulties while maintaining the thin package profile.
2Manufacturing precision
If the independent terminals are etched before mounting the semiconductor chip, then the terminal pattern can be formed, but external forces cause the location of the independent terminals to deviate from desired positions making alignment difficult
Solution Approach 1:
The patent reverses the conventional sequence by performing chip mounting on the intact leadframe with protruding terminals before etching. This allows precise alignment to be established on the stable, unetched leadframe, and the terminal pattern is subsequently formed without disturbing the already-established alignment.
3Ease of manufacture
If the independent terminals, insulating material, and semiconductor chip are combined with different thermal expansion coefficients, then the package can be manufactured, but warpage occurs during the molding step resulting in delamination
Solution Approach 1:
The patent performs chip mounting before molding, allowing the chip to be securely attached to the leadframe while the structure is still accessible. This preliminary bonding creates a more robust assembly that better withstands the thermal stresses of subsequent molding, reducing warpage and delamination risks.
4Length of moving object
If the very thin leadframe is used, then the package thickness is reduced, but the independent terminals are left unsupported except for the insulation material which is very limited and ineffective
Solution Approach 1:
The patent secures the chip to the thin leadframe before etching, providing mechanical support to the leadframe structure. This preliminary support prevents the thin leadframe from deforming or breaking during the etching process, maintaining terminal strength without requiring additional insulation material support.
Data Source
AI summary
In one embodiment, a method for forming an electronic package structure includes providing a single unit leadframe having first terminals on a first or top surface. An electronic device is attached to the single unit leadframe and electrically connected to the first terminals. The leadframe, first terminals, and the electronic device are encapsulated with an encapsulating material. Second terminals are then formed by removing portions of a second or bottom surface of the leadframe. In one embodiment, the method can be used to fabricate a thin substrate chip scale package (“tsCSP”) type structure.