Thin Substrate Package Method for Electronic Components
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current wafer level packaging methods face limitations in yield and material cost due to the inability to pre-test intermediate layers and the complexity of integrating multiple elements, leading to inefficient packaging processes and high material waste.
Innovation Solution
A package method for electronic components using a thin substrate that involves forming metal and dielectric layers, parting the substrate from a carrier, performing tests to identify and select defect-free package units, and connecting chips via flip chip bonding, followed by molding, allowing for improved yield and reduced material costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer level packaging is performed on the entire silicon wafer before dicing, then the packaging process can be completed in bulk, but defects in the multi-layer substrate cannot be detected until after dicing, causing yield loss
Solution Approach 1:
The patent divides the wafer into multiple individual package units on the multi-layer substrate, allowing each unit to be tested independently before final packaging. This segmentation enables selective packaging of good units while discarding defective ones, resolving the contradiction between bulk packaging efficiency and yield protection.
Solution Approach 2:
The patent implements pre-packaging testing of the multi-layer substrate at the wafer level before final dicing and packaging. This preliminary action allows defects to be detected early, enabling selective packaging decisions that improve overall yield while maintaining efficient bulk processing capabilities.
2Ease of manufacture
If the multi-layer substrate is manufactured on a silicon wafer and then diced after molding, then the entire wafer can be processed uniformly, but defective package units cannot be selected and discarded, leading to material waste
Solution Approach 1:
The patent performs testing and identification of defective package units on the multi-layer substrate before the final dicing step. This preliminary identification allows defective units to be marked for discarding, ensuring that only good units proceed to final packaging and dicing, thereby minimizing material waste while maintaining uniform processing for good units.
Solution Approach 2:
The patent enables the discarding of defective package units identified during pre-packaging testing, while recovering and packaging only the good units. This selective discarding and recovery approach reduces material waste from defective units while maintaining efficient processing of good units.
3Adaptability or versatility
If Fan-out WLP techniques are used to increase pad area, then more components can be integrated, but the package size and complexity increase
Solution Approach 1:
The patent uses a multi-layer substrate that serves multiple functions: it provides mechanical support, electrical interconnection, and thermal management for multiple different types of electronic components (IC chips, passive components, sensors). This universal substrate design enables high component integration while maintaining a unified, manageable package structure rather than increasing overall complexity.
Data Source
AI summary
Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.