Thin Wafer Handling via Recessed Substrate Nesting
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Solution Overview
Problem
Current methods for handling, packaging, and testing of microelectronic devices and interposer structures face challenges in minimizing size while ensuring electrical interconnection reliability, particularly in compact arrangements required for portable devices and data servers.
Innovation Solution
A method involving the alignment of microelectronic elements with substrates having recesses, where electrically conductive bumps are reflowed to liquefy and solidify within these recesses, forming mechanical and electrical connections, and allowing for efficient handling, testing, and potential stacking of microelectronic elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If chips are thinned to reduce package height, then the overall height of the microelectronic package is reduced, but handling and testing of the thin chips becomes difficult
Solution Approach 1:
The patent places the thinned chip inside a recess of the package substrate, creating a nested structure where the chip is housed within a cavity. This nesting approach provides mechanical support and protection for the thin chip during handling and testing, while still achieving the goal of reduced overall package height.
Solution Approach 2:
The patent introduces a non-wettable layer as an intermediary between the solder bump and the recess wall. This intermediary layer prevents unwanted solder flow onto the recess wall while still allowing the solder to form a reliable connection, thereby facilitating easier handling and testing of the thinned chip.
2Area of stationary object
If chips are stacked to minimize planar area, then the area occupied on the circuit panel is reduced, but the complexity of interconnections and alignment increases
Solution Approach 1:
The patent implements a stacked chip arrangement where multiple chips are vertically arranged one on top of another, each chip nested within the structure of the previous layer. This vertical nesting minimizes the planar area occupied while maintaining organized interconnections through aligned recesses and conductive elements.
Solution Approach 2:
The patent applies different surface properties to different regions of the recess - the inner surface has a non-wettable layer to control solder flow, while specific areas allow for controlled solder attachment. This local differentiation of surface properties simplifies the interconnection process in stacked arrangements by preventing solder bridging while ensuring reliable connections.
3Reliability
If recesses are created in the substrate to contain reflowed bumps, then mechanical engagement reliability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies a non-wettable coating only to the inner surface of the recess where solder contact is not desired, while leaving other areas unaffected. This localized application of different surface properties achieves reliable mechanical engagement through controlled solder containment without requiring complex manufacturing processes for the entire substrate.
Solution Approach 2:
The patent forms the non-wettable layer on the recess inner surface before the solder reflow process. This preliminary action pre-configures the surface to control solder flow during reflow, ensuring reliable mechanical engagement while simplifying the overall manufacturing process by preventing the need for complex real-time control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more compact microelectronic assemblies with reliable electrical interconnections, facilitating the integration of multiple chips in small spaces and enhancing the bandwidth and power efficiency of complex devices.
Implementation Method 1
The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein
Data Source
AI summary
A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.