Thin Wafer Polishing Stop Layer for Uniform Substrate Thinning
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Solution Overview
Problem
Existing stack-type semiconductor devices face challenges in achieving uniform thickness and preventing damage to conductive members during the thinning process, which is crucial for reducing device size and signal transmission path length.
Innovation Solution
The implementation of a polishing stop layer with an insulation trench structure, arranged symmetrically or in regions with rapid polishing speeds, to control the polishing process and ensure uniform thickness without damaging conductive structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the wafer is thinned to reduce device size and signal transmission path length, then the device size and signal transmission path length are reduced, but the uniformity of thickness and integrity of conductive members deteriorate
Solution Approach 1:
A polishing stop layer is formed in advance at a predetermined depth from the front surface of the substrate before the thinning process. This stop layer acts as a pre-established reference point that guides the polishing process, ensuring that the substrate is thinned to the correct thickness while maintaining uniformity across the wafer surface.
Solution Approach 2:
The polishing stop layer serves as an intermediary element between the polishing process and the substrate. It mediates the thinning process by providing a controlled stopping point, preventing over-polishing, and ensuring that conductive members are not damaged while achieving the desired thickness reduction.
2Volume of moving object
If the wafer is thinned to reduce device size and signal transmission path length, then the device size and signal transmission path length are reduced, but the integrity of conductive members deteriorates
Solution Approach 1:
The polishing stop layer is formed in advance at a depth that ensures conductive members remain protected during the thinning process. By establishing this stop layer before polishing begins, the process automatically stops before reaching the conductive members, preventing their damage while achieving the desired device size reduction.
Solution Approach 2:
The polishing stop layer acts as a protective intermediary that shields conductive members from the polishing process. It absorbs the mechanical action of polishing, allowing the substrate to be thinned safely without compromising the integrity of the conductive structures beneath.
3Productivity
If conventional polishing is used to thin the wafer, then the thinning process can be performed, but polishing uniformity deteriorates and damage to conductive members occurs
Solution Approach 1:
The polishing stop layer is formed at specific locations and depths within the substrate, creating local variations in polishing resistance. This local quality difference allows the polishing process to proceed uniformly across the wafer surface, as the stop layer provides consistent reference points that guide material removal and ensure uniform thickness reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively improves polishing uniformity, allowing for the formation of thin substrates with uniform thickness and preventing damage to conductive members, thereby enhancing the manufacturing of thin wafers and stack-type semiconductor devices.
Implementation Method 1
polishing the bottom surface of the semiconductor substrate until the polishing stop layer is exposed
Data Source
AI summary
In an embodiment, a wafer may include a substrate including a first surface and a second surface opposite to each other, a polishing stop layer formed in a selected portion of the substrate, the polishing stop layer including one or more insulation trenches each filled with an insulation material and having a depth corresponding to a thickness of the substrate, and a device layer supported by the substrate and structured to include a plurality of conductive patterns configured to electrically connect different circuit elements in the substrate.


