Thinned Channel MOS Transistor Fabrication
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Solution Overview
Problem
The thinning of source and drain regions during the fabrication of CMOS transistors leads to increased external resistance due to reduced silicon seed availability and limited cross-sectional area, resulting in decreased transistor performance.
Innovation Solution
A process is developed where the silicon body is initially formed thicker and wider, allowing for controlled thinning of the channel region while maintaining the thickness and width of the source and drain regions, using techniques such as ion implantation, spacer formation, and selective etching to reduce the channel region dimensions without affecting the source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the source and drain regions are thinned during fabrication, then the channel region can be reduced in size, but the external resistance increases due to reduced cross-sectional area
Solution Approach 1:
The patent segments the silicon body into distinct regions with different thicknesses: the channel region is thinned to a first thickness while the source and drain regions maintain a second thickness greater than the first. This is achieved through selective etching processes that remove silicon material from the channel region while preserving the source and drain regions, thereby reducing channel size without compromising external resistance.
Solution Approach 2:
The patent applies local quality by creating non-uniform thickness distribution across the silicon body. The channel region has a reduced thickness optimized for device performance, while the source and drain regions maintain greater thickness to ensure low resistance. This localized differentiation allows each region to be optimized for its specific function without compromising overall device reliability.
2Length of moving object
If the silicon body is thinned to create small channel regions, then transistor scaling is achieved, but yield loss occurs due to insufficient silicon seed availability
Solution Approach 1:
The patent employs preliminary action by forming a thicker silicon body before patterning and etching operations. This initial thicker body provides sufficient silicon seed material throughout the manufacturing process, ensuring that even after selective thinning of the channel region, adequate material remains in the source and drain regions. This approach prevents yield loss while enabling the creation of scaled-down channel regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the external resistance of the transistors by maintaining thicker source and drain regions, thereby enhancing transistor performance and preventing yield loss associated with prior art processing methods.
Implementation Method 1
using techniques such as ion implantation, spacer formation, and selective etching to reduce the channel region dimensions
Implementation Method 2
using techniques such as ion implantation, spacer formation, and selective etching to reduce the channel region dimensions without affecting the source and drain regions
Data Source
AI summary
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.