Thinned Channel Semiconductor Device with Local Quality
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Solution Overview
Problem
In fully depleted semiconductor-on-insulator (SOI) devices, achieving a thin channel thickness for improved electrostatics and short channel control is challenging due to low process margins and increased extension resistance, which can result in the channel region being cut off from the source/drain region.
Innovation Solution
A method involving forming a dummy gate and sidewall spacers, followed by thinning the semiconductor layer to create a thinned channel region with a thickness of 50-75% of the original, allowing for a thicker extension region and lower extension resistance, while maintaining a replacement gate stack with a lower portion extending below the sidewall spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thin channel thickness is used to improve electrostatics and short channel control, then device performance is improved, but process margins are reduced and extension resistance increases
Solution Approach 1:
The patent applies local quality by creating a thinned channel region with different thickness than the extension region. The channel region under the gate is thinned to 50-75% of the original thickness to improve electrostatics, while the extension regions adjacent to the source and drain maintain the original thicker thickness to provide process margins and reduce extension resistance. This spatial variation in thickness resolves the contradiction between electrostatics control and manufacturing precision.
2Reliability
If a thin channel thickness is used to improve electrostatics, then short channel control is improved, but extension resistance increases
Solution Approach 1:
The patent implements local quality by differentiating the channel thickness in two distinct regions: the channel region under the gate stack is thinned to improve short channel control, while the extension regions are maintained at greater thickness to reduce extension resistance. This localized thickness variation allows simultaneous optimization of both short channel control and extension resistance characteristics.
Data Source
AI summary
A method for making a semiconductor device may include forming a dummy gate above a semiconductor layer on an insulating layer, forming sidewall spacers above the semiconductor layer and on opposing sides of the dummy gate, forming source and drain regions on opposing sides of the sidewall spacers, and removing the dummy gate and underlying portions of the semiconductor layer between the sidewall spacers to provide a thinned channel region having a thickness less than a remainder of the semiconductor layer outside the thinned channel region. The method may further include forming a replacement gate stack over the thinned channel region and between the sidewall spacers and having a lower portion extending below a level of adjacent bottom portions of the sidewall spacers.