Thinned Charge Storage Layer for 3D Memory Integration
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Solution Overview
Problem
The challenge lies in achieving low-cost, mass-production of three-dimensional (3D) semiconductor devices that maintain or exceed the operational reliability of their two-dimensional (2D) counterparts, while increasing integration density to meet consumer demands for superior performance and affordability.
Innovation Solution
The semiconductor device design includes a stack of insulating patterns vertically stacked on a substrate with gate patterns interposed between them, an active pillar passing through the stack and electrically connected to the substrate, and a charge storing layer with specific thickness and protruding portions, along with blocking insulating regions and a tunnel insulating layer, fabricated using alternating layers and oxidation processes to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional (3D) semiconductor devices are fabricated to increase integration density, then integration density is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The charge storing layer is divided into multiple portions with different thicknesses: a first portion adjacent to the gate pattern, a second portion adjacent to the insulating pattern, and a thinned third portion between them. This segmentation allows different functional zones within the same layer to optimize both charge storage and manufacturing feasibility
Solution Approach 2:
Different regions of the charge storing layer are given different thicknesses to perform different functions: the first and second portions maintain sufficient thickness for reliable charge storage, while the third portion is thinned to reduce interference and improve manufacturability in specific localized areas
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables improved charge retention and reliability in 3D semiconductor devices by reducing vertical charge spreading, thus enhancing the integration density and operational performance while maintaining cost-effectiveness for mass production.
Implementation Method 1
a charge storing layer interposed between the stack and the active pillar
Implementation Method 2
fabricated using alternating layers and oxidation processes
Data Source
AI summary
A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.