Thinned FinFET Extension Portions Reduce Leakage
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Solution Overview
Problem
Field effect transistors (FETs) face challenges in reducing source-drain leakage current and process complexity due to gate length variation penalties in direct printing and additional lithography steps required for self-aligned-double-patterning (SADP) processes, especially at advanced generations like 7NM and beyond.
Innovation Solution
The method involves forming a finFET with thinned extension portions of the fin, where the channel portion has a first width and the extension portions have a second width less than the first, achieved through etching and additional doping, which reduces source-drain leakage current and avoids the complexities of SADP and direct printing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If direct printing with single mask is used to pattern Wimpy devices, then gate length can be controlled, but gate length variation increases
Solution Approach 1:
The gate pattern is divided into two segments: the main gate region patterned by the first mask, and the extended gate region patterned by the second mask. This segmentation allows each mask to be optimized for its specific region, reducing overall gate length variation while maintaining control over the total gate length.
Solution Approach 2:
The first mask patterns the main gate region in advance, establishing a stable reference structure. Then the second mask adds the extended gate region in a subsequent step, allowing the extension to be controlled independently without affecting the main gate dimensions, thereby reducing gate length variation.
2Manufacturing precision
If SADP process is used to form Wimpy devices, then gate length control is improved, but process complexity increases
Solution Approach 1:
The patterning process is segmented into two independent lithography steps with two separate masks, where each mask defines a specific portion of the gate. This approach achieves the gate length control benefits of SADP while avoiding its complexity by using straightforward mask-based patterning for each region.
Solution Approach 2:
The patent introduces an intermediary extended gate region that connects the main gate to the channel, allowing independent control of gate length through separate masking. This intermediary structure simplifies the overall patterning process compared to SADP while maintaining precise gate length control.
3Object-generated harmful factors
If gate length is increased to reduce source-drain leakage, then leakage current decreases, but device performance degrades
Solution Approach 1:
The gate structure has different widths at different locations: a narrower main gate region over the channel for high performance, and an extended gate region for leakage control. This local quality variation allows the device to simultaneously achieve low leakage current and high performance without the trade-off.
Solution Approach 2:
Instead of controlling leakage solely through gate length (one dimension), the patent extends the gate in the lateral dimension while maintaining different widths along the gate length dimension. This multi-dimensional approach allows independent optimization of leakage control and device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases source-drain leakage current and increases threshold voltage while maintaining gate critical dimension stability, reducing process complexity and variability, and is applicable to both nFET and pFETs in system-on-chip designs.
Implementation Method 1
Thinning the extension portions may include etching the extension portions of the fin with a wet etch or a dry etch.
Implementation Method 2
The additional doping may be performed with a Boron and Phosphorous family dopant. The additional doping may have a dopant concentration in range of approximately 1E18 cm−3 to approximately 1E21 cm−3.
Data Source
AI summary
A method of manufacturing a field effect transistor includes forming a fin on a substrate, forming source and drain electrodes on opposite sides of the fin, forming a gate stack on a channel portion of the fin between the source and drain electrodes, forming gate spacers on extension portions of the fin on opposite sides of the gate stack, removing at least a portion of the gate spacers to expose the extension portions of the fin, and thinning the extension portions of the fin. Following the thinning of the extension portions of the fin, the channel portion of the fin has a first width and the extension portions of the fin have a second width less than the first width.