Selectively Thinned GAA Nanoribbons for Memory Write Error Mitigation
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Solution Overview
Problem
Designing semiconductor devices that consume less energy is challenging, especially at lower voltage levels, as they become susceptible to process and dopant variations, leading to potential write errors in memory cells.
Innovation Solution
The technique involves selectively thinning the semiconductor regions of p-channel devices compared to n-channel devices in gate-all-around (GAA) transistors, reducing the width of p-channel nanoribbons to lower the operating current and mitigate write errors, by forming a dielectric helmet during etching and subsequent processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If voltage scaling techniques are employed to decrease energy consumption, then energy consumption is reduced, but the semiconductor devices become more susceptible to process and dopant variations causing malfunction
Solution Approach 1:
The patent applies different channel widths to different transistor types within the same circuit. Specifically, p-channel transistors are given narrower channels while n-channel transistors have wider channels, creating local variations in device characteristics to optimize both low-voltage operation and reliability
Solution Approach 2:
The invention changes the physical parameter of channel width selectively for different transistor types. By reducing the channel width of p-channel transistors relative to n-channel transistors, the patent adjusts the current characteristics to maintain proper voltage levels and reduce susceptibility to process variations
2Reliability
If the width of p-channel nanoribbons is reduced to lower operating current, then write errors are mitigated, but the device complexity increases due to selective thinning processes
Solution Approach 1:
The patent incorporates the selective thinning of p-channel nanoribbons into the initial fabrication sequence. Helmet structures are formed and etching processes are applied during the standard manufacturing flow, preparing the differentiated channel widths before final device assembly, thus integrating complexity into earlier process steps
Solution Approach 2:
The invention uses helmet structures as intermediary elements during fabrication. These temporary structures enable selective protection of certain nanoribbon regions during etching, allowing precise control over which channels are thinned without requiring complex direct patterning of each individual channel
Data Source
AI summary
Techniques are provided herein to form semiconductor devices having thinned semiconductor regions (e.g., thinner nanoribbons) compared to other semiconductor devices on the same substrate and at a comparable height (e.g., within same layer or adjacent layers). In an example, neighboring semiconductor devices of a given memory cell include a p-channel device and an n-channel device. The p-channel device may be a GAA transistor with a semiconductor nanoribbon having a first width while the n-channel device may be a GAA transistor with a semiconductor nanoribbon having a second width that is larger than the first width (e.g., first width is half the second width). The p-channel device may have a thinner width than the corresponding n-channel device in order to structurally lower the operating current through the p-channel devices by decreasing the width of the active semiconductor channel.