Thinned Gate Spacers for Independent PMOS Performance Modulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuits face challenges in modulating the performance of PMOS and NMOS devices independently, as simultaneous gate size adjustments affect both types of devices, leading to unintended performance changes.
Innovation Solution
The method involves forming PMOS devices with different dummy spacer thicknesses to modulate performance without affecting NMOS devices, using epitaxy stressors to apply varying stresses and adjust saturation currents, while maintaining independent control over PMOS and NMOS device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate sizes of PMOS and NMOS devices are adjusted to modulate performance, then device performance can be customized, but the performance of the other device type is adversely affected
Solution Approach 1:
The patent segments the gate structure into two independent components: a common gate formed simultaneously for both PMOS and NMOS devices, and separate dummy gates that can be independently adjusted. This segmentation allows performance modulation of one device type without affecting the other, as the dummy gates can be selectively modified based on circuit requirements.
Solution Approach 2:
The patent applies local quality by making the gate structures non-uniform through selective dummy gate adjustment. Different regions of the gate (common vs. dummy portions) have different functions and can be optimized independently, allowing customized performance characteristics for specific device types while maintaining standard performance for others.
2Power
If gate sizes are increased to improve device performance, then saturation current can be enhanced, but leakage current increases
Solution Approach 1:
The patent changes the physical parameters of the gate structure by introducing dummy gates with adjustable dimensions, materials, and positions. By modifying these parameters selectively, the patent optimizes saturation current enhancement while controlling leakage current, achieving better power characteristics without the trade-offs of uniform gate size increases.
3Ease of manufacture
If simultaneous gate formation is used for PMOS and NMOS devices, then manufacturing process is simplified, but independent performance control is lost
Solution Approach 1:
The patent applies preliminary action by forming a common gate structure first that serves both PMOS and NMOS devices, then subsequently adding or modifying dummy gates based on specific performance requirements. This sequential approach maintains the simplicity of simultaneous formation while enabling independent customization in a second stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for independent modulation of PMOS device performance without increasing leakage currents and minimizes the impact on NMOS device performance, enabling tailored performance in different circuit regions.
Implementation Method 1
forming PMOS devices with different dummy spacer thicknesses to modulate performance without affecting NMOS devices, using epitaxy stressors to apply varying stresses and adjust saturation currents
Data Source
AI summary
A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance.