Thinned Junction Semiconductor Structures for ESD Protection
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Solution Overview
Problem
Advanced silicon on insulator (SOI) technologies face challenges with electrostatic discharge (ESD) protection due to increased input/output operating voltages, lower device failure voltages, and higher frequency input/outputs requiring lower capacitance solutions, which standard double diode ESD protection structures cannot adequately address, especially in field-effect transistors (FETs) with silicide blocking that increase capacitance and hinder gate silicidation for enhanced electrical contact.
Innovation Solution
The method involves forming doped extension regions in semiconductor structures with a thicker channel portion under a gate of a field-effect transistor (FET), where these regions are bounded by a dielectric material rather than oppositely doped semiconductor material, allowing for increased sheet resistance and reduced capacitance by minimizing the interface between extension regions and oppositely doped semiconductor material, and preventing silicide formation on extension regions while allowing it on the gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicide blocking is used on extension regions to increase sheet resistance for ESD protection, then ESD performance is improved, but capacitance at the interface between extensions and P-well increases significantly
Solution Approach 1:
The patent extracts the harmful interface by removing the P-well semiconductor material directly beneath the extension regions and replacing it with an insulator material. This extraction eliminates the capacitance-causing interface between oppositely doped semiconductor materials while preserving the extension regions for ESD protection functionality.
Solution Approach 2:
The patent introduces an insulator material as an intermediary between the extension regions and the P-well. This insulator layer acts as a mediator that electrically isolates the extension regions from the P-well, thereby eliminating the parasitic capacitance while allowing the extension regions to maintain their ESD protection function through silicide blocking.
2Reliability
If a single silicide blocking mask shape extends from drain to source, then ESD characteristics are improved, but the ability to silicide the gate for enhanced electrical contact is prohibited
Solution Approach 1:
The patent segments the silicide blocking arrangement by using separate mask regions: a first mask region for blocking silicide on extension regions and a second mask region for allowing silicide on the gate. This segmentation enables independent control of silicide formation on different device regions, resolving the conflict between ESD protection and gate electrical contact enhancement.
Solution Approach 2:
The patent applies silicide blocking selectively to specific locations rather than uniformly across the entire device. By applying silicide blocking only to extension regions and permitting silicide formation on the gate, the patent creates local quality differences that optimize both ESD characteristics and electrical contact properties in their respective regions.
3Device complexity
If extension regions are formed with oppositely doped semiconductor material interfaces, then device structure is simplified, but capacitance at the interface increases which is undesirable in high speed designs
Solution Approach 1:
The patent extracts the harmful interface by removing the oppositely doped semiconductor material interface directly beneath the extension regions and replacing it with an insulator material. This extraction eliminates the capacitance-causing interface while maintaining the overall device structure simplicity.
Data Source
AI summary
A method of forming a semiconductor structure, including forming a channel in a first portion of a semiconductor layer and forming a doped extension region in a second portion of the semiconductor layer abutting the channel on a first side and abutting an insulator material on a bottom side. The first portion of the semiconductor layer is thicker than the second portion of the semiconductor layer.