Thinned Semiconductor Fin via Laterally Receded Hard Mask
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Solution Overview
Problem
The continuous miniaturization of metal-oxide-semiconductor field effect transistor (MOSFET) devices poses challenges in conventional transistor structures, particularly in achieving desirable control over the transistor channel, as seen in surrounding gate structures which are difficult to realize in practice.
Innovation Solution
The development of a semiconductor device fabrication process involving a semiconductor fin structure with a laterally reduced dielectric hard mask, achieved through a plasma etch using fluorocarbon etchants like octofluoro butane and hexafluoro cyclobutene, allows for the formation of a thinned semiconductor fin with improved gate control, enabling smaller feature sizes and enhanced transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional MOSFET structures are continuously miniaturized, then transistor density increases, but control over the transistor channel deteriorates
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change allows the gate to control the channel from multiple sides (front and back gates), providing superior electrostatic control over the channel while maintaining small footprint, thus resolving the contradiction between high density and good gate control.
Solution Approach 2:
The patent implements nested gate structures where inner and outer gates are positioned at different heights around the vertical fin channel. The inner gate is surrounded by the outer gate, creating a nested configuration that enables independent control of different channel regions while maintaining compact space utilization, thereby achieving both high density and precise control.
2Manufacturing precision
If surrounding gate structures are used to improve channel control, then gate control precision improves, but device complexity increases
Solution Approach 1:
The patent divides the gate structure into separate front gate and back gate components that can be formed and controlled independently. This segmentation allows each gate to be optimized and controlled separately, simplifying the manufacturing process compared to a fully integrated surrounding gate, while still achieving superior channel control through the combined effect of both gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enables the creation of smaller transistor features, improving gate control and addressing the challenges of miniaturization, leading to higher performance and lower power consumption in semiconductor devices.
Implementation Method 1
a plasma etch using fluorocarbon etchants like octofluoro butane and hexafluoro cyclobutene
Implementation Method 2
plasma etch using fluorocarbon etchants like octofluoro butane and hexafluoro cyclobutene
Data Source
AI summary
A process may include forming a mask directly on and above a region selected as an initial semiconductor fin on a substrate and reducing the initial semiconductor fin forming a semiconductor fin that is laterally thinned from the initial semiconductor fin. The process may be carried out causing the mask to recede to a greater degree in the lateral direction than the vertical direction. In various embodiments, the process may include removing material from the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded mask. Electronic devices may include the thinned semiconductor fin as part of a semiconductor device.