Third Metal Gate Stack for CMOS Interconnection
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Solution Overview
Problem
In semiconductor manufacturing, there is a challenge in forming reliable interconnections between different regions on a semiconductor substrate with high conductivity while preventing short circuits and ensuring minimal material usage, especially when connecting n-type and p-type field effect transistors.
Innovation Solution
A third type of metal gate stack is introduced, comprising an n-type workfunction metal layer, a p-type workfunction metal layer, and a low resistance metal layer, positioned above an isolation structure between replacement metal gate n-type and p-type field effect transistors, which can be used for local connections, engineering transistor behavior, or reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal gate stack is formed to connect n-type and p-type field effect transistors, then electrical interconnection is achieved, but resistance in the interconnection increases
Solution Approach 1:
The patent applies composite materials by forming a metal gate stack consisting of multiple metal layers with different properties. The first metal layer provides work function engineering for transistor threshold voltage control, while the second metal layer provides low resistance for electrical interconnection. This composite structure resolves the contradiction by combining materials with complementary properties to achieve both reliable switching and low resistance connection.
Solution Approach 2:
The metal gate stack structure serves multiple functions simultaneously: it acts as a gate electrode for transistor switching, provides electrical interconnection between transistors, and enables work function engineering. The first metal layer handles the work function requirement while the second metal layer handles the low resistance requirement, allowing the single gate structure to fulfill multiple competing demands.
2Reliability
If interconnection material is used to connect regions, then electrical connection is established, but material usage increases leading to higher parasitic capacitance
Solution Approach 1:
The metal gate stack serves dual purposes: as the gate electrode controlling transistor switching and as the interconnection material connecting transistors. By making the gate structure itself conductive through the second metal layer, the patent eliminates the need for separate interconnection material, thereby reducing material quantity and associated parasitic capacitance while maintaining reliable electrical connection.
Solution Approach 2:
The patent merges the gate electrode function and interconnection function into a single integrated structure. The metal gate stack combines the gating function (through the first metal layer and gate dielectric) with the interconnection function (through the second metal layer), eliminating the need for separate interconnection elements and reducing overall material usage.
3Object-affected harmful factors
If gate height is reduced to minimize parasitic capacitance, then device performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses composite metal layers where the first metal layer (thinner, 1-5 nm) provides work function control and the second metal layer (thicker, 5-20 nm) provides low resistance and structural robustness. This composite approach allows reduced overall gate height to minimize capacitance while the thicker second layer maintains manufacturing tolerances and process robustness.
Solution Approach 2:
Different regions of the gate structure have different thicknesses and material compositions optimized for their specific functions. The first metal layer is thinner and positioned where work function control is needed, while the second metal layer is thicker where low resistance and mechanical stability are needed. This local optimization allows reduced overall gate height without compromising manufacturing precision.
Data Source
AI summary
A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.